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LP-AM243: PRU EXTERNAL SOURCE INTERRUPT

Yüksel Zengin
Prodigy 40 points

Part Number: LP-AM243
Other Parts Discussed in Thread: SYSCONFIG, UNIFLASH

Tool/software:

Hello,

I am dealing with PRU interrupt and task manager. While the PRU core is running in the main while loop, I want the task manager to be triggered by an interrupt, suspend task0, and execute to task2 . My first problem is how to assign an external source, such as a button, to the PRU interrupt. It can be configured via the Syscfg under the ICSSG0 INTC Internal Signals Mapping by selecting the 112: PRU_ICSSG0_PR1_SLV_IN_48 event signal, but how can I map this to a GPIO input button? I have seen the GPIOMUX Interrupt Router registers. How can I configure this within the PRU?

My second question is how to trigger the task manager when an interrupt occurs. I do not want to poll the R31 register value in the while loop. The code should be interrupted at the point of execution and switch to task2 when the interrupt comes, and after task2 finishes, it should continue from where it left off.

I would be very grateful if you could help me with these two questions. I have read the GPIO MUX INTERRUPTER, PRU-ININTC, and TASK MANAGER sections in the TRM in detail multiple times and reviewed other related questions in the forum but could not reach a conclusion. I would appreciate it if you could help in more detail.

Best Regards



 

  • 0 in reply to Yüksel Zengin
    TI__Expert 7395 points

    Hi,

    Can you help me with a few questions for a better understanding of your use case:

    1. Do you want to use main domain GPIO to trigger an interrupt to the PRU?

    2. You want to do above configuration in the PRU code without using sysconfig?

    Please correct me if my understanding is wrong.

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Hello ,

    First of all, thank you for trying to help. I want an interrupt to be triggered in the PRU when a signal on a GPIO pin falls from high to low. In the interrupt, I plan to activate Task2 and run it. I need to monitor the signal status of this GPIO pin on pru, until Task2 is completed . Once Task2 is finished, I plan to clear the interrupt register to be able to receive new interrupts and exit.

    While trying to set up an external interrupt source for PRU INITC, I came across the gpiomux interouter and thought I could do it with this. However, I couldn't find out how to do it. I would appreciate your help.

    If possible, I would like to configure these settings through the sysconfig interface.

    Thank you.
  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Hello again, 


    While researching the GPIOMUX introuter, I came across the Resource Partition and from this page:
    https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/latest/exports/docs/api_guide_am243x/RESOURCE_ALLOCATION_GUIDE.html

    I went ahead and opened the interface below, but is it the right place for what I want to do and what value should I give to the tabs here ?

    I would be glad if you could help me, have a nice day.


  • 0 in reply to Nitika Verma
    Prodigy 40 points



    I want to connect the GPIO interrupt to PRU_ICSSG0_PR1_SLV_IN _[46] :

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Hi ,

    Are the details enough? I hope I could explain the problem. I am in a bit of a hurry due to the project delivery. I would be very happy if you could help me.
    Slight smile

  • 0 in reply to Yüksel Zengin
    TI__Expert 7395 points

    Hi,

    I understand your use case, let me share my understanding below:

    Allow me some time to test the solution for this and get back to you.

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Hi ,

    Yes, the design I want to make is similar to what you drew, thank you. Is there any progress ?

    Regards

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Hi,

    https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/latest/exports/docs/api_guide_am243x/RESOURCE_ALLOCATION_GUIDE.html

    According to the guide above, I activated the icssg0 core and increased the Main GPIO Interrupt Router Count value and generated it.

    The following code snippets were then added to the sciclient_defaultBoardcfg_rm.c file:


    ...
    ...
    {
    .host_id = TISCI_HOST_ID_ICSSG_0,
    .allowed_atype = 0b101010,
    .allowed_qos = 0xAAAA,
    .allowed_orderid = 0xAAAAAAAA,
    .allowed_priority = 0xAAAA,
    .allowed_sched_priority = 0xAA
    },
    ...
    ...
    ...

    {
    .num_resource = 12,
    .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    .start_resource = 18,
    .host_id = TISCI_HOST_ID_ICSSG_0,
    },

    Then I enabled the gpio interrupt and pru from the syscfg interface:






    Later when I build the project, in the ti_drivers_config.c file :

    static void Sciclient_gpioIrqSet(void)
    {
    int32_t retVal;
    struct tisci_msg_rm_irq_set_req rmIrqReq;
    struct tisci_msg_rm_irq_set_resp rmIrqResp;
    rmIrqReq.valid_params = 0U;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event = 0U;
    rmIrqReq.src_id = TISCI_DEV_GPIO1;
    rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(33);
    rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
    rmIrqReq.dst_host_irq = CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_0;
    rmIrqReq.ia_id = 0U;
    rmIrqReq.vint = 0U;
    rmIrqReq.vint_status_bit_index = 0U;
    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
    if(0 != retVal)
    {
    DebugP_log("[Error] Sciclient event config failed!!!\r\n");
    DebugP_assert(FALSE);
    }
    return;
    }


    The code is coming. The target core is not pru, it creates r core.



  • 0 in reply to Yüksel Zengin
    TI__Expert 7395 points

    Hi,

    The above issue is what I am currently looking at. You will not be able to set PRU as the destination core using sysconfig because only the the host_irq linked with R5F core can be added in an application designed for the R5F core.

    No changes will be needed with the Resource partitioning tool. The below changes should be sufficient:

    1. Comment out the functions calling Sciclient_gpioIrqSet and Sciclient_gpioIrqRelease, copy the content of the commented out functions to new functions in your application (add the required #define to the application as well).

    2. Make the following changes:

    • rmIrqReq.dst_id = TISCI_DEV_PRU_ICSSG0;
      rmIrqReq.dst_host_irq = CSLR_PRU_ICSSG0_PR1_SLV_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_38;

    3. The sysconfig settings should be as following:

         

         ...

         

    Note: I have not tested the above the changes on my setup yet, I will need some time to do that.

    You can try these and check on your end if you wish.


    For configuring the Task Manager, this section of the TRM explains how to use it - PRUICSSG_TASK_MANAGER

    Also, the ADS85x8 ADC example in the SDK (C:\ti\mcu_plus_sdk_am243x\examples\pru_io\adc\ads85x8\firmware) utilises the Task manager as well.

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 40 points
    Nitika Verma said:

    Kaynak bölümleme aracıyla hiçbir değişikliğe gerek kalmayacak. Aşağıdaki değişiklikler yeterli olacaktır:

    1. Sciclient_gpioIrqSet ve  Sciclient_gpioIrqRelease fonksiyonlarını yorum satırına alın  , yorum satırına alınan fonksiyonların içeriklerini uygulamanızdaki yeni fonksiyonlara kopyalayın (gerekli #define'ı da uygulamaya ekleyin).

    2. Aşağıdaki değişiklikleri yapın:

    • rmIrqReq.dst_id = TISCI_DEV_PRU_ICSSG0;
      rmIrqReq.dst_host_irq = CSLR_PRU_ICSSG0_PR1_SLV_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_38;

    Thank you very much for your answer.
    I will work on it while you try it. I will comment out the functions in ti_drivers_config.c and add their contents to the main code that will run in R core and build it. However, during build , syscfg will regenerate ti_drivers_config.c and the Sciclient_gpioIrqSet and Sciclient_gpioIrqRelease functions will be regenerated. So these functions will be to uncomment.  Am I misunderstanding this?.

  • 0 in reply to Yüksel Zengin
    TI__Expert 7395 points

    You need not make any changes to the auto-generated file.

    In your application, there should be a function like Board_gpioInit() or any other name that calls Sciclient_gpioIrqSet internally, you need to comment out that function call in the application.

    You can refer to gpio_input_interrupt_am243x-evm_r5fss0-0_nortos_ti-arm-clang example which has a similar implementation. 

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Thank you Nitika, I will try it.

    Regards

  • 0 in reply to Yüksel Zengin
    TI__Expert 7395 points

    Hi,

    I discussed your use case internally. In addition to the above changes, SBL changes will be needed as well.

    Please refer to the steps here - e2e.ti.com/.../lp-am243-lp-am243

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Hello,

    I have reviewed it here and based on this I tried to make the settings with the Resource partitioning tool but as I mentioned above, the following changes are made to the sciclient_defaultBoardcfg_rm.c file : 


    ...
    ...
    {
    .host_id = TISCI_HOST_ID_ICSSG_0,
    .allowed_atype = 0b101010,
    .allowed_qos = 0xAAAA,
    .allowed_orderid = 0xAAAAAAAA,
    .allowed_priority = 0xAAAA,
    .allowed_sched_priority = 0xAA
    },
    ...
    ...
    ...

    {
    .num_resource = 12,
    .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    .start_resource = 18,
    .host_id = TISCI_HOST_ID_ICSSG_0,
    },

    ...
    ...
    ...

    Here for icssg0 core, gpiomux introuter starts from 18. but according to trm it starts from 38 (MAIN_GPIOMUX_INTROUTER0_OUTP_38).

    How can we solve this problem?

     

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Hi,

    I did what you said, but when I run r core I get this error:

    [MAIN_Cortex_R5_0_0] [Error] Sciclient event config failed!!!
    ASSERT: 0.15607s: ../main.c:Sciclient_gpioIrqSet:62: FALSE failed !!!


    main.c code:


    #include <stdlib.h>
    #include "ti_drivers_config.h"
    #include "ti_board_config.h"

    #include <stdio.h>
    #include <drivers/sciclient.h>
    #include <drivers/hw_include/am64x_am243x/cslr_intr_pru_icssg0.h>

    #define TISCI_BANK_SRC_IDX_BASE_GPIO0 (90U)
    #define TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U)
    #define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (30U)

    static void Sciclient_gpioIrqSet(void);

    int main(void)
    {
    System_init();
    Board_init();

    Drivers_open();
    Board_driversOpen();

    Sciclient_gpioIrqSet();

    DebugP_log("All tests have passed!!\r\n");

    Board_driversClose();
    Drivers_close();

    Board_deinit();
    System_deinit();

    return 0;
    }

    static void Sciclient_gpioIrqSet(void)
    {
    int32_t retVal;
    struct tisci_msg_rm_irq_set_req rmIrqReq;
    struct tisci_msg_rm_irq_set_resp rmIrqResp;
    rmIrqReq.valid_params = 0U;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event = 0U;
    rmIrqReq.src_id = TISCI_DEV_GPIO1;
    rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(31);
    rmIrqReq.dst_id = TISCI_DEV_PRU_ICSSG0;
    rmIrqReq.dst_host_irq = CSLR_PRU_ICSSG0_PR1_SLV_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_38;
    rmIrqReq.ia_id = 0U;
    rmIrqReq.vint = 0U;
    rmIrqReq.vint_status_bit_index = 0U;
    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
    if(0 != retVal)
    {
    DebugP_log("[Error] Sciclient event config failed!!!\r\n");
    DebugP_assert(FALSE);
    }
    return;
    }

  • 0 in reply to Yüksel Zengin
    TI__Expert 7395 points

    Hi,

    I tested the R5F side implementation and it is working for me. Please follow the steps below:

    Yüksel Zengin said:
    {
    .num_resource = 12,
    .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    .start_resource = 18,
    .host_id = TISCI_HOST_ID_ICSSG_0,
    },

    1. In the file you get from the resource partitioning tool, replace the above segment with the below code

    {
    .num_resource = 1,
    .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    .start_resource = 38,
    .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},

    2. Save the file and run the below command to re-build the board configuration

    make -s -C tools/sysfw/boardcfg sciclient_boardcfg SOC=am243x

    3. Compiling the SBL by running the below commands inside the MCU+ SDK folder

    make -s -C examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang clean
make -s -C examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang 
make -s -C examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang clean PROFILE=debug
make -s -C examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang PROFILE=debug

    4. Replace the sbl_null image present in <mcu_plus_sdk>/tools/boot/sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage with the new generated image.

    5. Flash your board with the new sbl_null image, following the steps here - FLASH_SOC_INIT

    6. Power up the board and load the example again from CCS. It should work.


    Once you get this configuration working, it means the Interrupt router has been configured properly. You can continue with the Task manager implementation.

    Attaching the file below for reference:

    Fullscreen 7356.sciclient_defaultBoardcfg_rm.c Download 
    /*
 * K3 System Firmware Resource Management Configuration Data
 * Auto generated from K3 Resource Partitioning tool
 *
 * Copyright (c) 2018-2023, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/**
 *  \file sciclient_defaultBoardcfg_rm.c
 *
 *  \brief File containing the rm boardcfg default data structure to
 *      send TISCI_MSG_BOARD_CONFIG_RM message.
 *
 */
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <drivers/sciclient.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_hosts.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_boardcfg_constraints.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_devices.h>

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* \brief Structure to hold the RM board configuration */
struct tisci_local_rm_boardcfg {
    struct tisci_boardcfg_rm      rm_boardcfg;
    /**< Board configuration parameter */
    struct tisci_boardcfg_rm_resasg_entry resasg_entries[TISCI_RESASG_ENTRIES_MAX];
    /**< Resource assignment entries */
};

const struct tisci_local_rm_boardcfg gBoardConfigLow_rm
__attribute__(( aligned(128), section(".boardcfg_data") )) =
{
    .rm_boardcfg = {
        .rev = {
            .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
            .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
        },
        .host_cfg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
                .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_host_cfg),
            },
            .host_cfg_entries = {
                {
                    .host_id = TISCI_HOST_ID_M4_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_ICSSG_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
            },
        },
        .resasg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
                .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
            },
            .resasg_entries_size = 166 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
        },
    },
    .resasg_entries = {
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 28,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 32,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 14,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 38,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
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        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
            .start_resource = 2,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 22,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 26,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 28,
            .host_id = TISCI_HOST_ID_ALL,
        },
    }
};

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    Hello ,

    Thank you for the answer.

    Nitika Verma said:

    1. In the file you get from the resource partitioning tool, replace the above segment with the below code

    I did what you said, sciclient_defaultBoardcfg_rm.c file:

    Fullscreen 1256.sciclient_defaultBoardcfg_rm.c Download 
    /*
 * K3 System Firmware Resource Management Configuration Data
 * Auto generated from K3 Resource Partitioning tool
 *
 * Copyright (c) 2018-2023, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/**
 *  \file sciclient_defaultBoardcfg_rm.c
 *
 *  \brief File containing the rm boardcfg default data structure to
 *      send TISCI_MSG_BOARD_CONFIG_RM message.
 *
 */
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <drivers/sciclient.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_hosts.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_boardcfg_constraints.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_devices.h>

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* \brief Structure to hold the RM board configuration */
struct tisci_local_rm_boardcfg {
    struct tisci_boardcfg_rm      rm_boardcfg;
    /**< Board configuration parameter */
    struct tisci_boardcfg_rm_resasg_entry resasg_entries[TISCI_RESASG_ENTRIES_MAX];
    /**< Resource assignment entries */
};

const struct tisci_local_rm_boardcfg gBoardConfigLow_rm
__attribute__(( aligned(128), section(".boardcfg_data") )) =
{
    .rm_boardcfg = {
        .rev = {
            .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
            .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
        },
        .host_cfg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
                .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_host_cfg),
            },
            .host_cfg_entries = {
                {
                    .host_id = TISCI_HOST_ID_M4_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_ICSSG_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
            },
        },
        .resasg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
                .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
            },
            .resasg_entries_size = 166 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
        },
    },
    .resasg_entries = {
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 28,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 32,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 14,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 38,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 4,
            .host_id = TISCI_HOST_ID_M4_0,
        },
        {
            .num_resource = 41,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_TIMESYNC_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 136,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
            .start_resource = 50176,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 12,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
            .start_resource = 18,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
            .start_resource = 26,
            .host_id = TISCI_HOST_ID_M4_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
            .start_resource = 27,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
            .start_resource = 48,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
            .start_resource = 54,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
            .start_resource = 60,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
            .start_resource = 62,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
            .start_resource = 66,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
            .start_resource = 28,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
            .start_resource = 34,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
            .start_resource = 42,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
            .start_resource = 46,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 12,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
            .start_resource = 18,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
            .start_resource = 26,
            .host_id = TISCI_HOST_ID_M4_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
            .start_resource = 27,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
            .start_resource = 6,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
            .start_resource = 14,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
            .start_resource = 18,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
            .start_resource = 6,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
            .start_resource = 14,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
            .start_resource = 18,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 14,
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        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
            .start_resource = 34,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
            .start_resource = 4,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
            .start_resource = 7,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
            .start_resource = 9,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
            .start_resource = 13,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
            .start_resource = 15,
            .host_id = TISCI_HOST_ID_M4_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
            .start_resource = 4,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
            .start_resource = 7,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
            .start_resource = 9,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
            .start_resource = 13,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
            .start_resource = 15,
            .host_id = TISCI_HOST_ID_M4_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 16,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 16,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
            .start_resource = 32,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
            .start_resource = 32,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
            .start_resource = 19,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
            .start_resource = 19,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
            .start_resource = 21,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
            .start_resource = 21,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
            .start_resource = 48,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
            .start_resource = 48,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
            .start_resource = 25,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
            .start_resource = 25,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
            .start_resource = 112,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
            .start_resource = 112,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
            .start_resource = 2,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 22,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 26,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 28,
            .host_id = TISCI_HOST_ID_ALL,
        },
    }
};


    Then I ran these commands:
    make -s -C tools/sysfw/boardcfg configure-gen SOC=am243x
    make -s -C tools/sysfw/boardcfg sciclient_boardcfg SOC=am243x


    make -s -C examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang clean
    make -s -C examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang
    make -s -C examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang clean PROFILE=debug
    make -s -C examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang PROFILE=debug

    Then I deleted the sbl_null.release.hs_fs.tiimage file in <mcu_plus_sdk>/tools/boot/sbl_prebuilt/am243x-lp/. Then  copiedsbl_null.release.hs_fs.tiimage from sdk_path\examples\drivers\boot\sbl_null\am243x-lp\r5fss0-0_nortos\ti-arm-clang to  and<mcu_plus_sdk>/tools/boot/sbl_prebuilt/am243x-lp/

    Nitika Verma said:
    5. Flash your board with the new sbl_null image, following the steps here - FLASH_SOC_INIT

    Then I tried to flash as shown here. After receiving the CCC.. string, I closed the terminal and ran the command python uart_uniflash.py -p COM6 --cfg=sbl_prebuilt/am243x-lp/default_sbl_null.cfg and got the following output:

    C:\ti\mcu_plus_sdk_am243x_09_02_00_50\tools\boot>python uart_uniflash.py -p COM6 --cfg=sbl_prebuilt/am243x-lp/default_sbl_null.cfg

    Parsing config file ...
    Parsing config file ... SUCCESS. Found 2 command(s) !!!

    Executing command 1 of 2 ...
    Found flash writer ... sending sbl_prebuilt/am243x-lp/sbl_uart_uniflash.release.hs_fs.tiimage
    Sent flashwriter sbl_prebuilt/am243x-lp/sbl_uart_uniflash.release.hs_fs.tiimage of size 303606 bytes in 28.15s.

    Executing command 2 of 2 ...
    Command arguments : --file=sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage --operation=flash --flash-offset=0x0
    Sending sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage: 0%| | 0/281797 [00:00<?, ?bytes/s]send error: expected NAK, CRC, EOT or CAN; got b'0'
    send error: expected NAK, CRC, EOT or CAN; got b'1'
    send error: expected NAK, CRC, EOT or CAN; got b'0'
    send error: expected NAK, CRC, EOT or CAN; got b'0'
    send error: expected NAK, CRC, EOT or CAN; got b'0'
    send error: expected NAK, CRC, EOT or CAN; got b'0'
    send error: expected NAK, CRC, EOT or CAN; got b'0'
    send error: expected NAK, CRC, EOT or CAN; got b'0'
    send error: expected NAK, CRC, EOT or CAN; got b'0'
    send error: error_count reached 10, aborting.
    Sending sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage: 0%| | 2/281797 [02:10<10205:25:15, 130.38s/bytes]
    [ERROR] XMODEM send failed, no response OR incorrect response from EVM OR cancelled by user,
    Power cycle EVM and run this script again !!!

    What could be the reason why I am getting this error? Can you help me?

  • 0 in reply to Yüksel Zengin
    TI__Expert 7395 points
    Yüksel Zengin said:
    make -s -C tools/sysfw/boardcfg configure-gen SOC=am243x

    Do not run this command after making changes to the sciclient_defaultBoardcfg_rm.c file. This command will overwrite your static changes.

    The file that you have shared above is correct. Save that file and build it using only this command - make -s -C tools/sysfw/boardcfg sciclient_boardcfg SOC=am243x



    Rest of the steps look fine. If you see the error again while flashing, please power cycle the board and try to flash again.

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 40 points

    What is meant by power cycle, turning the power off and on? I cut the power, plugged it in and repeated the same steps but got the same error.

  • 0 in reply to Yüksel Zengin
    TI__Expert 7395 points

    Yes, power cycle means turning the power off and on for the EVM. Just to confirm you are using the HS-FS version of the board right?

    Can you do one experiment for me, try flashing the default_sbl_ospi.cfg and see if you get the same error.

    If you don't get the error, it means something is wrong with your sbl_null file. You can try using the below file instead and try again

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/sbl_5F00_null.release.hs_5F00_fs.tiimage

    Regards,

    Nitika