Part Number: LP-AM243
Tool/software:
Hi TI
We just removed ethernet phy chip in am243x-lp board and coneected RGMII tx to RGMII rx channel to simply test mac2mac function. We successfylly received several frames and can enter EnetUdma_rxCqIsr , but after that we can no longer enter EnetUdma_rxCqIsr, but we can see rx registers is continuously growing larger and larger.

I think cpsw module has received the packages, but why interrupt handlers can not be generated? Which configuration need I check, please give some advice. Thanks very much.
We are using enet_lwip_cpsw example in SDK, we found that the other net port are not working well when this happen, we ping it but get no response after this happed.
We do more test and found that we can only receive 32 frames in our stack, if we send one frame per second, we will enter the error state in 32 seconds, if we send 100 frames in one second, we will enter the error state immediately.

When we change the number of packets field to 16, we can only receive 16 packets and then goto the error state.