AM2431: There is something unclear about TRM "6.2.3.4.1 R5FSS Power"

Hello 

Thank you for the query.

I need to check with the documentation expert.

Please expect some delay in response.

Regards,

Sreenivasa

Hi Sreenivasa,

 The R5F Sub-system, is based on a dual Core version of the R5F.  The words CPU and Core are used interchangeably through out the document. So Core0 or CPU0 refers to one of the R5F Cores, and Core1 or CPU1 refers to the other R5F Core.

 Our R5F implementation is a Split/Lock configuration. Because of this, when in Lock mode, there is a Primary Core (CPU), and a Redundant Core (CPU). Core0/CPU0 refers to the Primary Core/CPU, and Core1/CPU1 refers to the Redundant Core/CPU.

In Split mode, both Cores/CPUs can be used independently, but still Core0/CPU0 refers to the Primary Core/CPU, and Core1/CPU1 refers to the Redundant Core/CPU.

In the R5F Sub-system (and inside the R5F itself), there is logic that is related to the R5F Core0 (or CPU0), and logic that is related to the R5F Core1 (or CPU1).

From a power/reset controller point of view, CPU0 (and associated logic) should always be in a "higher state", than CPU1 (and associated logic).  In the RF5SS, what that means is CPU0 (and associated logic) can not be in reset while CPU1 (and associated logic) is out of reset.

Best Regards,

Abiel.

Hello Abiel,

Thank you for the inputs.

Regards,

Sreenivasa