Tool/software:
Can anyone please help me i am trying to write the uart(sci) dma code my tx is working but i am not getting anything in rx for reference i am posting my code please review and tell me what is the issue in my code
#include "sys_dma.h"
#include "sci.h"
#include "string.h"
// DMA control packet structures for TX and RX
g_dmaCTRL g_dmaCTRLPKT_TX;
g_dmaCTRL g_dmaCTRLPKT_RX;
volatile uint32 DMA_TX_Comp_Flag = 0xFFFFFFFF; // Initialize TX flag
volatile uint32 DMA_RX_Comp_Flag = 0xFFFFFFFF; // Initialize RX flag
// Function prototypes
void scidmaInit(void);
void scidmaSend(char *source_address);
void scidmaReceive(char *dest_address, uint32 length);
void sciNotification(sciBASE_t *sci, uint32 flags);
int main(void) {
// Initialize SCI and DMA
scidmaInit();
// Buffer to store received data
char received_data[100] = {0};
// Send test data over UART using DMA
char test_data[] = "Hello DMA UART Transfer!";
scidmaSend(test_data);
// Receive data over UART using DMA
scidmaReceive(received_data, strlen(test_data));
// Main loop
while (1) {
}
}
// Function to initialize DMA and SCI
void scidmaInit(void) {
// Initialize SCI for UART communication
sciInit(); // Initialize SCI module with default settings
// Initialize DMA
dmaEnable(); // Enable DMA controller
// Set up DMA control packet for RX (Receive) - **High priority, Channel 0**
g_dmaCTRLPKT_RX.SADD = (uint32)(&(scilinREG->RD)); // SCI Receive Data register
g_dmaCTRLPKT_RX.DADD = 0; // Destination address will be set later
g_dmaCTRLPKT_RX.FRCNT = 1; // Frame count: 1 byte/frame
g_dmaCTRLPKT_RX.ELCNT = 1; // Element count: 1 element/frame
g_dmaCTRLPKT_RX.RDSIZE = ACCESS_8_BIT; // Read size: 8-bit
g_dmaCTRLPKT_RX.WRSIZE = ACCESS_8_BIT; // Write size: 8-bit
g_dmaCTRLPKT_RX.TTYPE = FRAME_TRANSFER; // Frame-based transfer
g_dmaCTRLPKT_RX.ADDMODERD = ADDR_FIXED; // Source address is fixed (SCI RX register)
g_dmaCTRLPKT_RX.ADDMODEWR = ADDR_INC1; // Increment destination address
// Set the control packet for DMA Channel 0 (RX)
dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT_RX);
// Set up DMA control packet for TX (Transmit) - **Lower priority, Channel 1**
g_dmaCTRLPKT_TX.SADD = 0; // Source address will be set later
g_dmaCTRLPKT_TX.DADD = (uint32)(&(scilinREG->TD)); // SCI Transmit Data register
g_dmaCTRLPKT_TX.FRCNT = 1; // Frame count: 1 byte/frame
g_dmaCTRLPKT_TX.ELCNT = 1; // Element count: 1 element/frame
g_dmaCTRLPKT_TX.RDSIZE = ACCESS_8_BIT; // Read size: 8-bit
g_dmaCTRLPKT_TX.WRSIZE = ACCESS_8_BIT; // Write size: 8-bit
g_dmaCTRLPKT_TX.TTYPE = FRAME_TRANSFER; // Frame-based transfer
g_dmaCTRLPKT_TX.ADDMODERD = ADDR_INC1; // Increment source address
g_dmaCTRLPKT_TX.ADDMODEWR = ADDR_FIXED; // Destination address is fixed (SCI TX register)
// Set the control packet for DMA Channel 1 (TX)
dmaSetCtrlPacket(DMA_CH1, g_dmaCTRLPKT_TX);
// Set DMA channel 0 (RX) to trigger on hardware request (SCI RX request)
dmaReqAssign(30, 30); // SCI RX uses DMAREQ[30] (for Channel 0)
// Set DMA channel 1 (TX) to trigger on hardware request (SCI TX request)
dmaReqAssign(31, 31); // SCI TX uses DMAREQ[31] (for Channel 1)
// Enable DMA interrupts for both TX and RX completion
dmaEnableInterrupt(30, BTC); // RX DMA Channel 0 (higher priority)
dmaEnableInterrupt(31, BTC); // TX DMA Channel 1 (lower priority)
// Enable SCI TX and RX DMA requests (triggers DMA when SCI is ready)
scilinREG->SETINT = (1 << 16) | (1 << 17); // Enable SCI TX and RX interrupts for DMA
}
// Function to send data over SCI using DMA
void scidmaSend(char *source_address) {
// Wait for any previous DMA transfer to complete
while (DMA_TX_Comp_Flag != 0xFFFFFFFF);
// Reset the DMA completion flag
DMA_TX_Comp_Flag = 0xFFFFFFFF;
// Set the source address for the DMA transfer (the data to send)
g_dmaCTRLPKT_TX.SADD = (uint32)source_address;
// Set the number of bytes to transfer
g_dmaCTRLPKT_TX.FRCNT = strlen(source_address);
// Configure the DMA channel with the updated source address and frame count
dmaSetCtrlPacket(DMA_CH1, g_dmaCTRLPKT_TX); // TX on Channel 1
// Enable DMA channel 1 for hardware-triggered transfer
dmaSetChEnable(DMA_CH1, DMA_HW);
}
// Function to receive data over SCI using DMA
void scidmaReceive(char *dest_address, uint32 length) {
// Wait for any previous DMA transfer to complete
while (DMA_RX_Comp_Flag != 0xFFFFFFFF);
// Reset the DMA completion flag
DMA_RX_Comp_Flag = 0xFFFFFFFF;
// Set the destination address for the DMA transfer (the buffer to store received data)
g_dmaCTRLPKT_RX.DADD = (uint32)dest_address;
// Set the number of bytes to receive
g_dmaCTRLPKT_RX.FRCNT = length;
// Configure the DMA channel with the updated destination address and frame count
dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT_RX); // RX on Channel 0
// Enable DMA channel 0 for hardware-triggered transfer
dmaSetChEnable(DMA_CH0, DMA_HW);
}
// DMA interrupt handler for transfer completion
void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) {
if (channel == DMA_CH0) {
DMA_RX_Comp_Flag = 0x99BBCCDD; // RX DMA completed
} else if (channel == DMA_CH1) {
DMA_TX_Comp_Flag = 0x55AAD09E; // TX DMA completed
}
}
