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Original question:

AM2732: How to configure MIBSPI for 8bit parallel, Max clock speed to interface to FPGA.

AM2732: I'd like to know constraints and limits of MIBSPI CLK Pin (MSS_MIBSPIA_CLK,RCSS_MIBSPIA_CLK)

Shumpei Tanaka
Prodigy 40 points
Part Number: AM2732

Tool/software:

I would like to know constraints and limits of MIBSPI CLK Pin shown below.

- Upper and lower limits of MIBSPI CLK in R5F core
- Upper and lower limits of MIBSPI CLK in DSP core
- constraints of MIBSPI CLK in R5F core
- constraints of MIBSPI CLK in DSP core
I imagine "constraints" is like "MIBSPI CLK has satisfy n-division of core frequency".

Contents I had investigate are in below.

a: It seems like that Upper limits is 25MHz.

`- The maximum clock rate supported over each MIBSPI module is 25 MHz.`
- [MIBSPI Peripheral JAJSNL7 datasheet | TI.com](www.ti.com/.../datasheet

`- The maximum clock rate supported over each MIBSPI module is 25 MHz.` from p64
- [AM2731CNSFHQNZNRQ1 datasheet(64/114 Pages) TI1 | AM273x SitaraTm Microcontrollers](www.alldatasheet.com/.../AM2731CNSFHQNZNRQ1.html)

- [AM2732: How to configure MIBSPI for 8bit parallel, Max clock speed to interface to FPGA. - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums](e2e.ti.com/.../am2732-how-to-configure-mibspi-for-8bit-parallel-max-clock-speed-to-interface-to-fpga)

b: It seems like that Upper limits is over 40MHz.

MIBSPI Performance
Internal loopback operation
Software/Application used : test_mibspi_performance
CPU: R5F
MIBSPI Clock: 40MHz

CPU: C66
MIBSPI Clock: 40MHz

- from [MIBSPI Performance AM273x MCU+ SDK: Datasheet](software-dl.ti.com/.../DATASHEET_AM273X_EVM.html

c: others I had read.

below is I had read and cannot found infomation I need.

[AM273x Technical Reference Manual](www.ti.com/.../spruiu0d.pdf
p2283 `11.1.4 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP)`
p2294 `11.1.4.2.7 Clocking Modes`

- [AM273x MCU+ SDK: MIBSPI](software-dl.ti.com/.../DRIVERS_MIBSPI_PAGE.html)

- [AM273x MCU+ SDK: APIs for MIBSPI](software-dl.ti.com/.../group__DRV__MIBSPI__MODULE.html)

Best regards.

  • +1
    TI__Mastermind 22685 points

    Hi,

    You can reference the Timing and Switching Characteristics section of the datasheet to determine the maximum allowable clock rate of the SPI interface.  When operating in SPI Master mode, the minimum output SPICLK cycle time generated is 40ns (25MHz).  When operating in SPI Slave mode, the minimum allowed input SPICLK cycle time is 25ns (40MHz).

    The above timings are regardless of whether it was the C66 or the R5F controlling the peripheral.

    Thanks,
    Mike

  • 0 in reply to Mike Pridgen
    Prodigy 40 points

    Hello Mr. Mike.

    Thank you for reply.

    I understand follows by your reply.
    - MIBSPI_CLK limits are written in Timing and Switching Characteristics section of the datasheet now.
    - MIBSPI_CLK limits are same in R5F and DSP core.
    - MIBSPI_CLK limits are below.
    - Master (Controller): 25MHz
    - Slave (Peripheral): 40MHz
    - There are no constraints like "MIBSPI CLK has satisfy n-division of core frequency".

    Sincerely.