LP-AM243: Accessing memory section directly instead of using RPMessages

coderAkdr

Part Number: LP-AM243

Tool/software:

Hello;

In motor control example I've seen some part;

struct pdo_tx_data {
uint16_t controlWord;
int8_t modeOfOperation;
int32_t targetPosition;
int32_t targetVelocity;
int16_t targetTorque;
};

struct pdo_rx_data {
uint16_t statusWord;
int8_t modeOfOperationDisplay;
int32_t actualPosition;
int32_t actualVelocity;
int16_t actualTorque;
};

/* Target data from the PLC */
__attribute__((section(".gTxDataSection"))) struct pdo_tx_data gTxData;
/* Actual data to send to the PLC */
__attribute__((section(".gRxDataSection"))) struct pdo_rx_data gRxData;

This means we can access some memory blocks form different cores and cast them into the structs. Therefore we can share data between different cores. Am I wrong?

I have 114 byte data need to share between cores ( r5 00-rf 10-r5 01-rf 11 and m4). I mean r5 00 sends 114 byte of data and receives different 114 byte in an order from all the others. When I use RPMessage for this it creates some latency that is I do not intent.

Can I all of this data into memory regions and read them from different cores? What are advantage/disadvantage of this approach while compared with RPMessage? Should I take care about race conditions between cores with this approach? Is it possible to share data between r5 cores and m4 core?

Regards
Kadir

11 months ago

0 Paula Carrillo 11 months ago

TI__Mastermind 38980 points

Hi Kadir, I am out of office today. I will come back to you at the end of the week. Feel free to ping me if you haven't gotten an answer by Friday

Thank you,

Paula

0 coderAkdr 11 months ago in reply to Paula Carrillo

Prodigy 210 points

Hello;

It is urgent issue, Is there someone can take care??

Regards
Kadir

0 Paula Carrillo 11 months ago in reply to coderAkdr

TI__Mastermind 38980 points

Hi Kadir, you can use shared memory for that. You can access same sections in MSRAM from different cores.

Additional details on how to create an empty multicore project AM243x academy: Multi-core projects. Here, every core has a non-overlapping MSRAM section, but you can add another MSRAM, something like below, that can be used for more than one core

/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM

One comment, is that if you are trying to write from R5F cores and read in M4 you would need to perform CacheP_wbInv()

(+) AM2434: Accessing MSRAM from M4FSS - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

I am not sure how this is done in motor control example (your above example), but probably, they are using MSRAM_NO_CACHE or USER_SHM_MEM for sharing PDO information

MSRAM_NO_CACHE : ORIGIN = 0x701C0000, LENGTH = 0x100

/* shared memories that are used by RTOS/NORTOS cores */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x00004000

thank you,

Paula

0 coderAkdr 10 months ago in reply to Paula Carrillo

Prodigy 210 points

Hi Paula;

I want to manage ethercat on 1 core and run each 1 motor on the other two cores. I want to transfer PDO information and other information (appr 200 bytes) via shared memory.

Do you think using IPC (RPMessage) is appropriate for this process or should the information be shared by accessing the memory directly between the cores?

There seems to be a latency problem in using IPC RPMessage. If direct memory access is followed, can IPC Notify be used to provide synchronization? In other words, IPC Notify + direct memory access and reading it. Do you have an example project that works this way? What do you recommend to prevent the data race concept in providing synchronization?

Regards
KAdir

0 coderAkdr 10 months ago in reply to coderAkdr

Prodigy 210 points

Reminder....!

0 Paula Carrillo 10 months ago in reply to coderAkdr

TI__Mastermind 38980 points

Hi Kadir,

coderAkdr said:
Do you think using IPC (RPMessage) is appropriate for this process or should the information be shared by accessing the memory directly between the cores?

if latency is a concern, then shared memory is a better option.

coderAkdr said:
If direct memory access is followed, can IPC Notify be used to provide

Yes, you can use IPC Notify with shared memory

coderAkdr said:
Do you have an example project that works this way? What do you recommend to prevent the data race concept in providing synchronization?

Please see AM243x MCU+ SDK: IPC Shared Memory Mutex using Spinlock (ti.com) this example uses shared memory to store the data that can be accessed by multiple cores in an atomic way by using spinlock to protect the shared memory access.

Other links as reference (in case it helps)

- Motor control: EtherCAT® Connected, Single-Chip, Dual-Servo Motor Drive Reference Design (ti.com). A bit more complex example, but it already uses PDO structure shared between cores

- AM243x MCU+ SDK: IPC Notify For basic information and API's

thank you,

Paula