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Original question:

AM2634-Q1: ucc5880-q1

AM2634-Q1: Use of ESM with multicore

Carwyn Griffiths
Prodigy 90 points

Part Number: AM2634-Q1
Other Parts Discussed in Thread: AM2634

Tool/software:

Hi,

I'm currently working on a project on the AM2634 which requires running two pairs of cores in lockstep, with the purpose being to allow one pair to continue running if the other fails. If both core pairs fail then the ESM should signal an external circuit to place the whole system in a safe state.

I'm looking at having the ESM set up to trigger a high priority interrupt and assert the SAFETY_ERRORn pin when any of the CCM events are triggered. If one core is still running it should receive the high priority interrupt and de-assert the SAFETY_ERRORn pin before the external circuit places the system in a safe state, if both cores have failed then the SAFETY_ERRORn pin should remain asserted.

The TRM and safety manual both state that to de-assert the SAFETY_ERRORn pin it is necessary that the event that caused the Error pin to assert must be cleared. If there is a CCM fault event, how can the other core clear this event? Is it necessary for the working core to reset the faulty core pair or do something similar?

Thanks,

Carwyn

  • 0
    TI__Guru**** 200276 points

    HI Carwyn,

    In case you get a CCM compare error, you need to run CCM-R5F selftest and CPU selftest to identify who causes the error. If the error is not fixed, writing "1" to ESM error status register will not clear the error flag, the error event to ESM will be still asserted. 

    The ESM status registers and ESM error pin control registers can be read and cleared from any CPU core. 

  • 0 in reply to QJ Wang
    Prodigy 90 points

    Hi,

    I'm not clear on the need to run self-tests after a compare error. Won't the ESM event that triggered the interrupt indicate the error source? 

    I'm more interested in how to clear a CCM fault when in the "Active Compare Mode" rather than in any of the self-test modes. 

    The problem I can see is that if one lock-stepped core pair fails the other core pair should be able to continue running the system, but if the ERROR pin cannot be de-asserted because the CCM is still outputting an error event to the ESM then the external safety circuit will place the whole system in a safe state. We are looking to have the external safety circuit used when both core pairs have failed, so would need to be able to clear the CCM fault if one core is still functioning correctly. 

  • 0 in reply to Carwyn Griffiths
    Prodigy 90 points

    Hi QJ Wang,

    Can you provide an update on the above?

    Thanks