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AM2632: How do I clear pending interrupts for ePWM

Daniel Brown
Prodigy 145 points
Part Number: AM2632

Tool/software:

Hello, I have set up an interrupt from ePWM that is triggered when counter equals CMPC while counting up.  I want it to generate one interrupt then go silent until needed again.

I tried waiting until I needed the interrupt to reset the Latched ePWM Interrupt (EPWMx_INT) Status Flag.

However, there is a problem.  Per register addendum documentation (spruj42c) table 3-532, 

Up to one interrupt can be pending while the
ETFLG[INT] bit is still set. If an interrupt is pending, it will not be
generated until after the ETFLG[INT] bit is cleared.

Because of this, as soon as I clear the interrupt Status Flag, the interrupt trips the ISR again.

I tried using EPWM_disableInterrupt(CONFIG_EPWM3_BASE_ADDR);

But it doesn't work.  Is there a way to clear pending interrupts so it won't trigger after I clear the Status Flag until the CMPC value is reached by the ePWM?

  • 0
    TI__Expert 3190 points

    Hi Daniel

    I apologize for the delayed response.

     EPWM_disableInterrupt() and then clearing the flag should technically work.

    I have contacted the dev to look into the functioning of this API, and see if it's working. I'll try to reproduce the error and get back to you by tomorrow.

    Regards,
    Akshit

  • 0 in reply to Akshit Pareek
    Prodigy 145 points

    What did you find out?

  • 0 in reply to Daniel Brown
    TI__Expert 3190 points

    Hi Daniel

    I tried to reproduce the issue by modifying the epwm_hr_duty_cycle example in the SDK, in the following way.

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    while(numIsrCnt > 0)
    {
    /* Temporarily disable interrupts for a specific window */
    if(numIsrCnt == 9900) {
    /* Disable and clear interrupts at start of window */
    EPWM_disableInterrupt(gEpwmBaseAddr);
    EPWM_clearEventTriggerInterruptFlag(gEpwmBaseAddr);
    numIsrCnt--;
    continue;
    }
    /* Skip ISR processing during interrupt disabled window (9900-9800) */
    if(numIsrCnt > 9800 && numIsrCnt < 9900) {
    numIsrCnt--;
    continue;
    }
    /* Re-enable interrupts at end of window */
    if(numIsrCnt == 9799) {
    EPWM_enableInterrupt(gEpwmBaseAddr);
    }
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    • Just tried to disable and enable interrupt again after a while.
    • Interrupt is generated at CMPC while counter is incrementing
    • numIsrCnt starts decrementing from 10000.

    This scenario executed properly and all tasks were passed.

    Could you share some more details on how you're trying to implement your scenario, I'll try to reproduce that issue.

    Meanwhile, let me know if this helps!

    Regards,
    Akshit

  • 0 in reply to Akshit Pareek
    Prodigy 145 points

    What I am trying to do is trigger an interrupt at CMPC = 10 counting up, every 100 cycles or so.  When the interrupt triggers, I do an operation and disable the interrupt.  Then after about 100 cycles, I clear the trigger and enable the interrupt. 

    What I see is that as soon as I clear the trigger and enable the interrupt, the ISR executes without waiting for the counter to get to CMPC counting up.

  • 0 in reply to Daniel Brown
    TI__Expert 3190 points

    Hi Daniel

    Could you try this project, I am replicating a similar scenario to yours, and it seems to be working fine.

    epwm_hr_duty_cycle_am263px-cc_r5fss0-0_nortos_ti-arm-clang.zip

    Regards,
    Akshit