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Original question:

AM2434: DDR parameters

AM2434: DDR parameters(con't)

Koichiro Tashiro
Mastermind 22915 points
Part Number: AM2434

Tool/software:

Hi,

This is additional questions to the original thread.
Based on the answer provided in the last post (below), the customer checked JEDEC (JESD79-4).

> all these values should be taken from the JEDEC spec, as the SoC interface will be compatible with those specs.  

But there is no values for DDR controller side to below parameters. 
tDASS : time between CLK output to DQS output
tIS, tIH : time between CLK output to ADR/CMD output
tDS, tDH : time between DQS output to DQ/DM output

How AM243x was validated to meet JEDEC spec?
If simulation was done, what values were used delay values for each timing?

Thanks and regards,
Koichiro Tashiro 

  • +1
    TI__Guru* 85820 points

    Koichiro, these values are optimized during training.  For example, write leveling will attempt to align the rising edge of DQS to the rising edge of CK.  And thus the tDSS/tDSH setup/hold times DQS falling to CK rising are met in the JEDEC spec.  So there won't be any values associated with those specs that we can give you.  Validation is performed and includes electrical compliance and functional validation across PVT.  All tests passed for AM64x/AM243

    Regards,

    James