TM4C1294NCPDT: Why Status of TX FIFO not full and TX FIFO empty both at logic 1?

Hi,

  You asked "Why Status of TX FIFO not full and TX FIFO empty both at logic 1?". This means the FIFO is empty and therefore TFE is set. Since the FIFO is empty, it is indirectly saying it is not FULL. The TNF bit is set when the TXFIFO is half or less than half full. When the FIFO is empty, it is less than half FULL. 

  When TXEOT is set, it means it has finished the current frame. 

The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely
and is only valid for Master mode devices/operations. This interrupt can be used to indicate when
it is safe to turn off the QSSI module clock or enter sleep mode. In addition, because transmitted
data and received data complete at exactly the same time, the interrupt can also indicate that read
data is ready immediately, without waiting for the receive FIFO time-out period to complete.

Note: In Freescale SPI mode only, a condition can be created where an EOT interrupt is generated
for every byte transferred even if the FIFO is full. If the the μDMA has been configured to
transfer data from this QSSI to a Master QSSI on the device using external loopback, an
EOT interrupt is generated by the QSSI slave for every byte even if the FIFO is full.