AM2432: Abnormal GPIO output of MCU

Hello zhanglongc

Thank you for the query.

Can you please provide information on the IOs that you are measuring the voltage?

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa:

      Sorry ,because the chinese Spring Festival holiday has just ended,the reply is a litte slow,I have selected two typical applications,and the test waveforms in follwing figure,GPIO V7 is initialized with a pull-up configuration,while GPIO W11 is initialized with pull-down configuration.Form the waveform,it can be seen that during the period when the SOC reset signal is released and the GPIO initialization is completed,GPIO has a floating level with an amplitude of about 500 mV and a duration of about 2-3 seconds.

     question:this is ok? it is other effect?

    Figure 1 GPIO V7 Power up   

   Figure 2 GPIO W11 power up 

Hello zhanglongc

Thank you for the inputs.

Are the GPIO11 and GPIO7 connected to any external IOs.

We recommend external pulls for any of the SOC IO that is connected to an attached device that could float.

In case these are not connected to any attached device, this is not a concern.

Please refer to the data sheet, LVCMOS specifications for the IO leakage. 

SOC IO buffers are off during reset and till the software enabled the required pull.

You might want to add the initialization of the pulls early in the software flow.

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa:

  1、Are the GPIO11 and GPIO7 connected to any external IOs

   Yes,Our system uses 2 SOC (AM2432) chips, where the GPIO V7 and GPIO W11 output of SOC1 is connected to the GPIO W12 and GPIO W11 output of SOC2.

 2、We recommend external pulls for any of the SOC IO that is connected to an attached device that could float.

   Our system uses multiple GPIO interconnects between SOC1 and SOC2. Does each GPIO need to perform a pull-up or pull-down operation? What would be the impact if we don't perform up and down pull.

3、Please refer to the data sheet, LVCMOS specifications for the IO leakage.

    You mean when we select PULL resisters need attention GPIO IO leakage?

4、SOC IO buffers are off during reset and till the software enabled the required pull.

     According to the data sheet, IO buffers are off after reset and till the software enabled the required pull，not only during reset.

Hello zhanglongc

Thank you.

zhanglongc said:

SOC IO buffers are off during reset and till the software enabled the required pull.

     According to the data sheet, IO buffers are off after reset and till the software enabled the required pull，not only during reset.

Let me rephrase

SOC IO buffers are off during reset, after reset and till the software enables the required pull.

zhanglongc said:

  1、Are the GPIO11 and GPIO7 connected to any external IOs

   Yes,Our system uses 2 SOC (AM2432) chips, where the GPIO V7 and GPIO W11 output of SOC1 is connected to the GPIO W12 and GPIO W11 output of SOC2.

Ok

zhanglongc said:

 2、We recommend external pulls for any of the SOC IO that is connected to an attached device that could float.

   Our system uses multiple GPIO interconnects between SOC1 and SOC2. Does each GPIO need to perform a pull-up or pull-down operation? What would be the impact if we don't perform up and down pull.

During reset, processor IO buffers are off and the IOs are in a high impedance state, effectively serving as an antenna that picks up noise. Without any termination, the IOs are in high impedance state. High impedance makes this easy for noise to couple energy on the floating signal trace and develop a potential that can exceed the recommended operating conditions, which creates an electrical over-stress (EOS) on the IOs. Electrostatic discharge (ESD) protection circuits inside the processor are designed to protect the device from handling before being installed on a PCB assembly.

zhanglongc said:

Please refer to the data sheet, LVCMOS specifications for the IO leakage.

    You mean when we select PULL resisters need attention GPIO IO leakage?

Correct.

Regards,

Sreenivasa

Hello zhanglongc

You mentioned you use 2 SOC. can you confirm if the SOC are powered from a common power source of individual PMICs.

If the supplies ramp at different times, you need to be aware of possible fail-safe violation.

Refer below FAQ

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1300808/faq-am625-am623-custom-board-hardware-design-power-sequencing-between-soc-processor-and-the-attached-devices-fail-safe

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa:

     Thank you reply a lot ,our system 2 SOC use a common power ,so 2  SOC supplies ramp at same time.according your reply, i understand the issue of the GPIO float voltage i tested  , if we didn't pull opration ,the problem can't solved.