[FAQ] AM625/AM623 Custom board hardware design – Power sequencing between SOC (Processor) and the Attached devices (Fail-safe)

Hi Board designers, 

Refer below inputs for the Power sequencing between SOC (Processor) and the Attached devices related queries.

Definitions 

What is a fail-safe IO pin?

* A fail-safe IO pin is designed so that external voltage can be connected to the IO terminal, even when the IO pin's power supply is turned off.
* An IO pins that is NOT fail-safe should never have external voltage applied to the pin when the IO pin's power supply is turned off.
* For more information about the valid input voltage range for both fail-safe and non-fail-safe pins, refer to the "Absolute Maximum Ratings" section of the processor's device tree.

1. Can I power the SOC (Processor) IOs and Attached devices from different power sources?

Most of the processor IOs are not fail-safe. Any time a peripheral device is powered from a different power source than the SOC, the peripheral must NEVER apply power to the IO pin that is outside of the valid input voltage range. The Power supply is required to be ramped and stable before the SOC (Processor) IOs are driven by external inputs.

Refer the data-sheet for information on available fail-safe IOs.  

2. Is there a recommended power sequencing requirement to be followed between the SOC (Processor) and the attached devices?

It is recommended to power the IOs of the external device from the same power source as the respective SOC (Processor) IOs to ensure the external device never applies potential to an SoC IO that is not powered. This is needed to protect the IOs of both devices.  

The core supply for the attached devices can be applied from an independent power source.

3. I have a modular design. I have the attached devices on the carrier board and the SOC (Processor) on the SOM board. Any power sequencing recommendations?

There are 2 possible options - the board designer needs to route the IO power rails from the SOM generated power supplies to the base board to power attached devices, or place the PMIC on the base board and route all of the supplies to the SOM.

4. Is there a recommendation to be followed when the SOC (Processor) and the attached devices are powered from different sources?

The interface signals between the SOC (Processor) and the attached device that could be driven to a voltage level outside of the recommended operating voltage, needs to be isolated using FET switches or FET BUS switches.

FET bus switches have been used in the Starter Kit design for other applications but these devices could be used for signal isolation. The FET bus switches are recommended to be enabled by an ANDing logic. The Power good output from the power sources of the SOC (Processor) and the attached device are the inputs to the FET bus switch.

5. Examples of failsafe IOs

Refer below summary of fail-safe IOs for AM625 

Refer to the below section of the data sheet

Specifications
Absolute Maximum Ratings 

Regards,

Sreenivasa