AM2434: AM243x

Jinlong Shen

Part Number: AM2434

Tool/software:

Hi there,

I am measuring sync0 and sync1 signals on J73 and J7.5 on AM243-LP board.
Sync0 cycle time appears to be 250 us on oscilloscope - this matches my expectation.
Sync1 cycle time appears to be 2 times the cycle time - this is problematic in my eyes.

Here the value of some CoE objects:
For your information: I see the following values with another tool in real-time.
SM output parameter is 0x1C32:01 is 0x02 and 0x1C32:02 is 250000, and
SM Input parameter is 0x1C33:01 is 0x03, and 0x1C33:02 is 250000.

Could you please help me understand why sync1 frequency is 500us instead of 250 us?

Best regards,
Jinlong

6 months ago

0 Harsha Begihally Shanmukhaswamy 6 months ago

TI__Intellectual 2860 points

Hello Jinlong Shen,

SYNC1 cycle time is multiple of SYNC0 cycle time, and this is the current design.

In TwinCAT > Device 2 (EtherCAT) > Box > EtherCAT (tab) > Advanced Settings > Distributed Clock, there is a section to configure SYNC1 cycle time.

Kind Regards,

0 Jinlong Shen 6 months ago in reply to Harsha Begihally Shanmukhaswamy

Intellectual 540 points

According to the values in 0x1C32 and 0x1C33 I am using DC sync mode : DC mode, shift of input latch with sync1. See ETG.1020 S(R) V1.4.0 Table 82. and section 23.1.1.5.1.3 shift of input latch with Sync1, Figure 30 and Figure 31. In both pictures, sync1 happens with the same cycle time as sync0 cycle time. Why is TI implementation different? How does TI determines how many multiples of sync0 cycle time should sync1 cycle time be?
I am willing to arrange NDA with you. May I get detailed description of TI design of EtherCAT slave stack for AM243?

0 Aaron Thomas 6 months ago in reply to Jinlong Shen

TI__Expert 8965 points

Hi Jinlong,

Can you share the wireshark logs from the initialization, for the above communication. Also please share the TwinCAT configuration in your case when the Time Period of Sync1 is double as that of Sync0.

The Sync1 configuration is done by the MainDevice (here TwinCAT). With the logs, we will be able to see how TwinCAT programs the corresponding registers.

Regards,
Aaron

0 Jinlong Shen 6 months ago in reply to Aaron Thomas

Intellectual 540 points

May I send it to you per Email?

0 Harsha Begihally Shanmukhaswamy 6 months ago in reply to Jinlong Shen

TI__Intellectual 2860 points

Hello Jinlong Shen,

You can attach the files/zip file here with Insert -> Image/video/file option.

Kind Regards,

0 Jinlong Shen 6 months ago in reply to Harsha Begihally Shanmukhaswamy

Intellectual 540 points

I don't want to have the data in the public. May I send it to you per Email?

0 Jinlong Shen 6 months ago in reply to Harsha Begihally Shanmukhaswamy

Intellectual 540 points

Thank you, mail is sent.

+1 Harsha Begihally Shanmukhaswamy 6 months ago in reply to Jinlong Shen

TI__Intellectual 2860 points

Hello Jinlong Shen,

We have analyzed the wireshark logs that you shared. The MainDevice is configuring the shift time in the SYNC1 Cycle Time Register (0x09A4 – 0x09A7):

SYNC0 Cycle Time Register (0x09A0): 250us

SYNC1 Cycle Time Register (0x09A4): 140us

In your configuration, if no shift time is configured for SYNC1 from MainDevice, then the SYNC1 cycle time will be same as SYNC0 cycle time of 250us.If there is a shift time configured for SYNC1, then the cycle time will be 500us (2*SYNC0), as you have observed, even if MainDevice is configuring SYNC1 cycle time to 1xSYNC0. We recommend you to remove the SYNC1 shift time in the configuration to get SYNC1 signal with cycle time identical to SYNC0.

This issue with the shift time will be addressed in the upcoming releases.

Kind Regards,

0 Jinlong Shen 6 months ago in reply to Harsha Begihally Shanmukhaswamy

Intellectual 540 points

I need more clarification:

I am shifting both sync0 and sync1. Now that you suggest me to remove shift of sync1, should I remove shift of sync0 as well?

Which mode of synchronization will I be using after the change? See ETG.1020 S(R) V1.4.0. I wish to know when I input data is being latched and when my output data is valid in a user application.

Best,
Jinlong

0 Jinlong Shen 6 months ago in reply to Jinlong Shen

Intellectual 540 points

Update:
I removed sync1 shift time. Indeed sync0 and sync1 now happens at the same time and at the same frequency.

I wish to the fix in the next release of TI SDK.

Arm-based microcontrollers

Arm-based microcontrollers forum

AM2434: AM243x