AM2634: ENET CPSW for multicore

Hi Anjana,

Can you provide more details on what conflicts are occurring?

The SoC can be configured so that data from each CPSW port is managed by a given core, however, initial configuration of the CPSW peripheral must be done only by a single core.

Best Regards,

Zackary Fleenor

Hi Fleenor,

My concern is that we cannot enable CPSW configurations in both cores simultaneously, correct? If we enable ENET_CPSW0, it includes both RGMII ports, but my requirement is to assign each RGMII port to a different core. However, since ENET_CPSW0 is shared, how can we properly handle this scenario?

Please correct me if my understanding is incorrect.

Hey Anjana,

What is meant by:

Anjana Ramalingam said:

assign each RGMII port to a different core

One core would be responsible for initial configuration of CPSW0, however any core can execute the associated API by using the EnetApp_acquirehandleInfo(). See AM263x MCU+ SDK: Enet Migration Guide for more information.

I will loop in our software expert to provide additional feedback.

Best Regards,

Zackary Fleenor

Hi Anjana,

As pointed out by Zack, only 1 core can configure CPSW. The syscfg wont let you design a system in such a way that you have two CPSW instances added (one for each core). Moreover, both the RGMII ports will also be linked to the core that will have the ENET CPSW0 added.

Do you mind explaining your application design and why do you want to specifically do one port handling on other core? Is the network application very CPU intensive?

Regards,
Shaunak

Hi Shaunak

I am a bit confused regarding the configuration of the CPSW (Ethernet switch) on the AM263x. My understanding is that a single instance of the CPSW can support two RGMII ports, and it is possible to configure one RGMII port on one core while configuring the second RGMII port on another core.

Based on Fleenor's explanation, my interpretation is as follows:

• One core should be responsible for initializing the CPSW by enabling CONFIG_ENET_CPSW0 and setting up Port 1 for use with one of the RGMII interfaces.
• Another core should then acquire access to the CPSW instance using EnetApp_acquireHandleInfo(), allowing it to configure and utilize Port 2 independently.

In our specific design, we have two different network applications running on separate cores. Each application is expected to use a dedicated Ethernet port for communication.

Could you confirm whether my understanding is correct or if there are any aspects I need to reconsider?

Hi Anjana

Let me discuss this with other Ethernet experts internally and get back by end of day or tomorrow first half.

Regards,
Shaunak

Hi Shaunak

Could you provide an update on the status of our issue? We would appreciate any new information or progress details regarding the matter.

Hi Anjana,

I would like to have an in-depth understanding of the use-case here. This can be possible but we don't have any out-of-box solution for it. I can give a high level overview, but first would like to visit the design. Can you share any block diagram or system use-case diagram which explains the ports being reserved for different R5F-cores?

If not over public forum, you can share it over email to me or in E2E personal chat as well.

Regards,
Shaunak

Hi Shaunak

I have provided a table listing the ports allocated to each core. These cores communicate with each other using Inter-Processor Communication (IPC). The table outlines the specific port assignments for each core, ensuring proper coordination and data exchange between them.

Kindly provide us with guidance on the next steps to proceed.

Hi Anjana,

I had a discussion with the team internally. A few follow up questions:

1. What ethernet applications do you run on two R5F cores?
2. What is the limitation in just 1 R5F core application handling all the requirement?
3. What are your throughput and latency requirements? (for both cores)
4. What is the maximum packet rate in your applications? (for both cores)

Regards,
Shaunak

Hi Shaunak

What Ethernet applications do you run on two R5F cores?

→ I will be running two different Ethernet server applications, each assigned to a separate R5F core. These servers will operate independently, ensuring that network communication for each application is handled separately. Each core will manage its respective Ethernet port, allowing for efficient and isolated processing of network traffic.

What is the limitation of using just one R5F core to handle all requirements?

→ A single R5F core managing both Ethernet server applications could lead to resource contention, increased processing load, and potential scheduling conflicts. By assigning each core to a dedicated Ethernet port, the system ensures isolated and efficient processing, prevents interference between servers, and enhances overall performance and reliability.

What are your throughput and latency requirements? (for both cores)

→ The system is designed to achieve a throughput of 1 Gbps while maintaining a latency of 50–200 µs per packet, ensuring efficient and high-speed Ethernet communication.

Hi Anjana,

Thanks for sharing the details, some points from my side:
1. Multi-core ethernet on MCU is complex because of current SW design and complexity.
2. Ambiguity in configuration, so by design it is recommended that only 1 core configure CPSW. Both cores should not access CPSW registers simultaneously. TI has some existing solutions (EthFW model) for multicore CPSW but that are not available for MCUs with no plans in near future to support it. EthFW design allows one core to be CPSW master and other are CSPW client cores (not present on AM26x MCUs). In EthFW, Master does all CSPW config, via IPC, clients send info to master if they want to change configuration.
3. On MCUs, this model is not available. (software-dl.ti.com/.../ethfw_c_ug_top.html)

There are two ways to proceed here:
1. Implement EthFW model to let Core-3 be Master and Core-4 be Client (open only DMA Channel by hardcoding flow ID). Call Enet DMA related functions wherever required. This might be complex, according to current roadmap, there are no plans to support this on AM26x MCUs. So this has to be driven on your end.
2. Based on some packet content, transfer the packets to other R5F core. Let one core handle all CPSW configs, transfer data to other core based on some packet content via IPC or LwIP bridge. One core does all the config and CPSW handling, other core can do data processing. This might add some software overhead but this is one possible and less complex solution.

Regards,
Shaunak