AM2634: CAN Rx Interrupt is as Message stored to Dedicated Rx Buffer but the bit corresponding to buffer is not being set in NDAT1 and NDAT2 registers

Hello,

I have a few questions to get started here.

1) What version of the AM263x MCU+SDK is being used?

2) Can you download and utlize CCS 12.8.1 (various bug fixes from 12.7.1)

3) I assume it is only the recieving node that expeciences this error?

4) Can you provide code snippets of the failing node CAN configuration?

5) Can you provide screenshots of the CAN_H/CAN_L and CANTX/CANRX signals at the time of failure?

6) What is the average time to failure?

7) Does the number of transmitting nodes have any effect on the TTF or Failure itself?

8) Would it be possilble to replace the current reciever node with an AM263xLaunchPad device and see if the error continues to occur?

Best Regards,

Zackary Fleenor

1)10.00.00.35

2)We have tried with CCS 12.8.1 but same issue was observed

3)No all nodes are getting this error

6)every 5s

7)yes, we are facing issue when more than 2 nodes are connected

8)No, it is custom hardware so it is not possible to connect launchpad as termination resistance will be changed if we connect launchpad

for other questions i am unable to answer right now.

Hello,

Thank you for providing this information.

The first thing I would suggest is updating to the latest MCU+SDK for AM263x v10.01.00.31 - (https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-r5FY9rRaGv/10.01.00.31/mcu_plus_sdk_am263x_10_01_00_31-windows-x64-installer.exe).

Are the transmitting nodes expected to receive any messages in the RX Buffer?

Scope shots of CAN_H/CAN_L and CANTX/CANRX will help to verify the actual data being sent on the bus.

Can you check the contents of RX Buffer itself and see if new data is present at the time of interrupt even if NDATx flag isn't being set?

Can share snippets of your CAN configuration?

Just to confirm my understanding, when the setup is working with only 2 nodes, this is the single receiver node and a single transmitter node? and once a 3rd transmitter node is added to the bus, every 5 seconds all nodes on the bus will experience the same RX Buffer Data Received interrupt (at the same time?) but NDATx flags do not reflect this?

This is interesting behavior, and unfortunately it is not possible for me to replicate the issue locally.

Best Regards,

Zackary Fleenor

Hi,

sorry for the delayed response

1) We will try with the new mcu plus sdk version

2)Are the transmitting nodes expected to receive any messages in the RX Buffer? Yes

3)

We read in TRM that this may occur in case of an error so to find the error we are also displaying the protocol status register which contains the details of the error and we found the error to be 01 ,by checking in trm we found this error is due to bit stuffing.

4)Just to confirm my understanding, when the setup is working with only 2 nodes, this is the single receiver node and a single transmitter node? and once a 3rd transmitter node is added to the bus, every 5 seconds all nodes on the bus will experience the same RX Buffer Data Received interrupt (at the same time?) but NDATx flags do not reflect this?

Ans: In our setup, there are 4 nodes : 3 can nodes are sending and receiving data and 1 node is only receiving data

Node 1 is sending message id 1 and receiving message id 4 and 7.

Node 2 is sending message id 4 and receiving message id 1 and 7.

Node 3 is only sending message id 7.

Node 4 is receiving message ids 1, 4 and 7.

Each node is experiencing some data loss but is not the same on every node at a particular time i.e if message id 4 is lost on node 1 , it is received correctly on node 2 at that time.

with two nodes (each sending and receiving simultaneously) , this issue was not observed (even if it was occurring, it was rare)

5)CAN Configuration snippets are provided below

---------------------------------------------------------------

void MCAN_SetConfig(Bool enableInternalLpbk)
{
MCAN_StdMsgIDFilterElement stdFiltElem[APP_MCAN_STD_ID_FILTER_CNT] = {0U};
MCAN_InitParams initParams = {0U};
MCAN_ConfigParams configParams = {0U};
MCAN_MsgRAMConfigParams msgRAMConfigParams = {0U};
MCAN_BitTimingParams bitTimes = {0U};
uint32_t i;

gMcanBaseAddr = (uint32_t) AddrTranslateP_getLocalAddr(APP_MCAN_BASE_ADDR);

/* Initialize MCAN module initParams */
MCAN_initOperModeParams(&initParams); //brs ??
/* CAN FD Mode and Bit Rate Switch Enabled */
#ifdef FD_MODE
initParams.fdMode = TRUE;
initParams.brsEnable = TRUE;
#else
initParams.fdMode = FALSE;
initParams.brsEnable = FALSE;
#endif

/* Initialize MCAN module Global Filter Params */
MCAN_initGlobalFilterConfigParams(&configParams);

/* Initialize MCAN module Bit Time Params */
/* Configuring default 1Mbps and 5Mbps as nominal and data bit-rate resp */
MCAN_initSetBitTimeParams(&bitTimes);

/* Initialize MCAN module Message Ram Params */
mcan_InitMsgRamConfigParams(&msgRAMConfigParams);

/* Initialize Filter element to receive msg, should be same as tx msg id */
// abh: make for more than 1 msg ids make a global array for recv msg ids
for (i = 0U; i < APP_MCAN_STD_ID_FILTER_CNT; i++)
{
mcan_InitStdFilterElemParams(&stdFiltElem[i], i);
}
/* wait for memory initialization to happen */
while (FALSE == MCAN_isMemInitDone(gMcanBaseAddr))
{}

/* Put MCAN in SW initialization mode */
MCAN_setOpMode(gMcanBaseAddr, MCAN_OPERATION_MODE_SW_INIT);
while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(gMcanBaseAddr))
{}

/* Initialize MCAN module */
MCAN_init(gMcanBaseAddr, &initParams);
/* Configure MCAN module Gloabal Filter */
MCAN_config(gMcanBaseAddr, &configParams);
/* Configure Bit timings */
MCAN_setBitTime(gMcanBaseAddr, &bitTimes);
/* Configure Message RAM Sections */
MCAN_msgRAMConfig(gMcanBaseAddr, &msgRAMConfigParams);
/* Set Extended ID Mask */
MCAN_setExtIDAndMask(gMcanBaseAddr, APP_MCAN_EXT_ID_MASK);

/* Configure Standard ID filter element */
for (i = 0U; i < APP_MCAN_STD_ID_FILTER_CNT; i++)
{
MCAN_addStdMsgIDFilter(gMcanBaseAddr, i, &stdFiltElem[i]);
}
if (TRUE == enableInternalLpbk)
{
MCAN_lpbkModeEnable(gMcanBaseAddr, MCAN_LPBK_MODE_INTERNAL, TRUE);
}

/* Take MCAN out of the SW initialization mode */
MCAN_setOpMode(gMcanBaseAddr, MCAN_OPERATION_MODE_NORMAL);
while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(gMcanBaseAddr));

return;
}

----------------------------------------------

void mcan_InitMsgRamConfigParams(MCAN_MsgRAMConfigParams
*msgRAMConfigParams)
{
int32_t status;

MCAN_initMsgRamConfigParams(msgRAMConfigParams);

/* Configure the user required msg ram params */
/* msgRAMConfigParams->lss = APP_MCAN_STD_ID_FILTER_CNT;
msgRAMConfigParams->lse = APP_MCAN_EXT_ID_FILTER_CNT;
msgRAMConfigParams->txBufCnt = APP_MCAN_TX_BUFF_CNT;
msgRAMConfigParams->txFIFOCnt = APP_MCAN_TX_FIFO_CNT;
// Buffer/FIFO mode is selected
msgRAMConfigParams->txBufMode = MCAN_TX_MEM_TYPE_BUF;
msgRAMConfigParams->txEventFIFOCnt = APP_MCAN_TX_EVENT_FIFO_CNT;
msgRAMConfigParams->rxFIFO0Cnt = APP_MCAN_FIFO_0_CNT;
msgRAMConfigParams->rxFIFO1Cnt = APP_MCAN_FIFO_1_CNT;
// FIFO blocking mode is selected
msgRAMConfigParams->rxFIFO0OpMode = MCAN_RX_FIFO_OPERATION_MODE_BLOCKING;
msgRAMConfigParams->rxFIFO1OpMode = MCAN_RX_FIFO_OPERATION_MODE_BLOCKING;
*/
/////munish changing mcan config ///////////////////////////

msgRAMConfigParams->flssa = (uint32_t)0U;
msgRAMConfigParams->lss = APP_MCAN_STD_ID_FILTER_CNT;
msgRAMConfigParams->flesa = (uint32_t)0U;
msgRAMConfigParams->lse = (uint32_t)0U; //APP_MCAN_STD_ID_FILTER_CNT;

msgRAMConfigParams->txStartAddr = (uint32_t)0U;
msgRAMConfigParams->txBufCnt = (uint32_t)32U;
msgRAMConfigParams->txFIFOCnt = (uint32_t)0U;
msgRAMConfigParams->txBufMode = (uint32_t)0U;

//event fifo optional fields as per internet
msgRAMConfigParams->txEventFIFOStartAddr = (uint32_t)0U;
msgRAMConfigParams->txEventFIFOCnt = (uint32_t)0U;
msgRAMConfigParams->txEventFIFOWaterMark = (uint32_t)0U;

//fifo 0 and 1 //start address should be specified
msgRAMConfigParams->rxFIFO0StartAddr = (uint32_t)0U;
msgRAMConfigParams->rxFIFO0Cnt = (uint32_t)0U;
msgRAMConfigParams->rxFIFO0WaterMark = (uint32_t)0U;
msgRAMConfigParams->rxFIFO0OpMode = (uint32_t)0U;
msgRAMConfigParams->rxFIFO1StartAddr = (uint32_t)0U;
msgRAMConfigParams->rxFIFO1Cnt = (uint32_t)0U;
msgRAMConfigParams->rxFIFO1WaterMark = (uint32_t)0U;
msgRAMConfigParams->rxFIFO1OpMode = (uint32_t)0U;

msgRAMConfigParams->rxBufStartAddr = (uint32_t)0U;
msgRAMConfigParams->rxBufElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams->rxFIFO0ElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams->rxFIFO1ElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams->txBufElemSize = MCAN_ELEM_SIZE_64BYTES;

status = MCAN_calcMsgRamParamsStartAddr(msgRAMConfigParams);
DebugP_assert(status == CSL_PASS);

return;
}

-------------------------------------------------------

void MCAN_initGlobalFilterConfigParams(MCAN_ConfigParams *configParams)
{
if (configParams != NULL)
{
/* Initialize MCAN Config params */
configParams->monEnable = (uint32_t)FALSE;
configParams->asmEnable = (uint32_t)FALSE;
configParams->tsPrescalar = (uint32_t)0xFU;
configParams->tsSelect = (uint32_t)FALSE;
configParams->timeoutSelect = MCAN_TIMEOUT_SELECT_CONT;
configParams->timeoutPreload = (uint32_t)0xFFFFU;
configParams->timeoutCntEnable = (uint32_t)FALSE;
/* Accept Non Matching Frames and Reject Remote frames */
configParams->filterConfig.rrfs = (uint32_t)TRUE;
configParams->filterConfig.rrfe = (uint32_t)TRUE;
configParams->filterConfig.anfe = (uint32_t)2U; // MCAN_RX_FIFO_NUM_1;
configParams->filterConfig.anfs = (uint32_t)2U; //MCAN_RX_FIFO_NUM_1;
}

return;
}

-----------------------------------------------------

Hello,

Thanks for sharing this additional information.

Bit stuffing is part of the CAN standard. It dictates that after every 5 consecutive bits of the same logical level, the 6th bit must be a complement. This is required to ensure the on-going synchronization of the network by providing rising edges. Further, it ensures that a stream of bits are not mis-interpreted as an error frame or as the interframe space (7 bit recessive sequence) that marks the end of a message. All CAN nodes automatically remove the extra bits.

If a sequence of 6 bits of the same logical level is observed on the bus within a CAN message (between the SOF and CRC field), the receiver detects this as a Bit Stuffing Error aka Stuff Error.

At this point scope shots of the CAN_H/CAN_L and CAN_TX/CAN_RX will be required in order to make any additional progress.

Can you also provide schematic details of the CAN bus connections for the 2-node configuration and the 4-node configuration?

Best Regards,

Zackary Fleenor

1) what exactly does scope shots mean?

2)I cannot share the exact schematics with you but we have provision for 20 nodes on a can bus with 120-ohm termination resistors (b/w P and N) on both far ends of the bus. On this bus we have connected two and four nodes with other nodes disconnected from the bus.

Is it possible to connect an oscilloscope probe to the CAN_H/CAN_L and CAN_RX/CAN_TX signals to get an idea of the signal integrity?

Would it be possible to implement split termination to provide additional filtering and stabilization of the common mode voltage?

Can you measure the resistance between CAN_H and CAN_L? (should be between 45 and 65 W to account for the tolerances within the CAN standard, the parallel impedance of the two termination resistors, and the input resistance of many nodes in parallel).

I also wanted to share a few documents TI has for additional information specifically related to this issue.

Controller Area Network Physical Layer Requirements - https://www.ti.com/lit/an/slla270/slla270.pdf

Basics of debugging the controller area network (CAN) physical layer - https://www.ti.com/lit/an/slyt529/slyt529.pdf

Critical Spacing of CAN Bus Connections - https://www.ti.com/lit/an/slla279a/slla279a.pdf

Best Regards,

Zackary Fleenor

Hi,

We were trying different things to resolve this issue so when we disabled brs and enabled transmission and reception on all 4 nodes we didn't get this error even after seeing them for 5 to 10 mins so i think this issue is not related to hardware/physical

.

Hello,

Glad to hear you were able to make some progress.

So, you disabled BRS (Bit Rate Switching), are you still using CAN-FD operation FDOE = 1?

Do the CAN transceivers on any of the given nodes support CAN-FD?

What specifically was done for the following statement?

TEMC said:

enabled transmission and reception on all 4 nodes

Thanks and Regards,

Zackary Fleenor