MSPM0L1306: Peripheral Register Access - Unexpected Interrupt for SPI Registers lower than 0x0800h offset

Antony Luton

Part Number: MSPM0L1306

Tool/software:

Dear Sir/Madam,

When ever I try to read or write to an SPI register < 0x800h offset, an "unexpected interrupt" occurs and the program sits in the

/* This is the code that gets called when the processor receives an unexpected  */
/* interrupt.  This simply enters an infinite loop, preserving the system state */
/* for examination by a debugger.                                               */
void Default_Handler(void)

How can I access these registers? ref TRM table Table 20-7. SPI Registers

Appreciate your assistance.

5 months ago

0 Yuhao Zhao 5 months ago

TI__Genius 9780 points

Which SPI register are you going to read/write? For L1306, SPI register offset is larger than 0x800h

0 Bruce McKenney 5 months ago in reply to Yuhao Zhao

Guru 99105 points

Thanks for the image, but I don't see this table in either the TRM (SLAU847D) or the data sheet (SLASEX0D). In the TRM, the SPI registers are listed in Table 20-7, and include a collection of things [CS1_POCI1, CPU_CONNECT_0, DMA_MAP_RX, e.g.] below 0x800.

[I was also curious about these at one time, but I could never get them to do anything, so I moved on.]

0 Antony Luton 5 months ago in reply to Bruce McKenney

Prodigy 75 points

Thanks Bruce for keeping an eye on my problems as well.

Question for Yuhao:

What version of TRM is the table 15-7 from? Is there a new version? SLAU847D says REVISED MAY2024, and a lot has happened since then.

Best regards,

Antony

+1 Yuhao Zhao 5 months ago in reply to Antony Luton

TI__Genius 9780 points

Sorry my document is out of date. I will have a test.

And could you share your code about how you access the registers.

0 Antony Luton 5 months ago in reply to Yuhao Zhao

Prodigy 75 points

Hi Sorry I clicked on the wrong button, how do un-select "This Resolved my issue"?

This is the debug screen shot:

unsigned int SPIPICORead;
SPIPICORead = *((uint32_t *) 0x40468008);

Best Regards,,

Antony

0 Yuhao Zhao 5 months ago in reply to Antony Luton

TI__Genius 9780 points

Thanks for sharing. I just tested it and MCU entered hardfault interrupt. It may be triggered by access invalid address. Now I am checking with team for the TRM registers.

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MSPM0L1306: Peripheral Register Access - Unexpected Interrupt for SPI Registers lower than 0x0800h offset