Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN
Tool/software:
Hello TI Support,
I am working on the TMS570LC4357 LaunchPad and trying to implement MibSPI1 data transmission using DMA. I have followed the TMS570LC43xx TRM (SPNU563A) and example threads on the E2E forums. However, the DMA seems not to transfer data to the MibSPI1 TX RAM. As a result, the data on the MOSI line appears as 0x00 consistently even though logic analyzer shows proper clock pulses.
My Setup:
MibSPI1 Master Mode (No loopback)
DMA TX from memory buffer to mibspiRAM1->tx[x].data
DMA RX from mibspiRAM1->rx[x].data to a memory buffer
TG0 (transfer group 0) configured with 10 elements
DMA channel 0 (RX), channel 1 (TX)
I’ve verified that manually writing to mibspiRAM1->tx[] works as expected, and data appears on the SIMO line
The Problem:
After enabling DMA (via dmaSetChEnable and mibspiTransfer()), the TX RAM of MibSPI1 remains filled with zeroes, indicating DMA did not write data
I’ve verified dmaEnable() is called, correct control packets are configured, and request lines (1 for TX, 0 for RX) are assigned
I tried both DMA_SW and DMA_HW triggering modes for testing
I also tried changing PORTASGN to both PORTA_READ_PORTB_WRITE and PORTB_READ_PORTA_WRITE, adjusting offsets, and toggling AUTOINIT
Despite all this, DMA does not write the data into MibSPI1 TX RAM. The FTC interrupt doesn't fire, and the transferred values are all zero on MOSI.
Request:
Can TI help identify what might be missing or incorrectly configured for DMA to MibSPI1 TX to work on TMS570LC4357?
I have attached my minimal working code here:
/** @file HL_sys_main.c
* @brief Application main file
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains an empty main function,
* which can be used for the application.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "HL_sys_common.h"
/* USER CODE BEGIN (1) */
#include <stdlib.h>
#include <string.h>
#include "HL_mibspi.h"
#include "HL_gio.h"
#include "HL_sys_dma.h"
/* USER CODE END */
/** @fn void main(void)
* @brief Application main function
* @note This function is empty by default.
*
* This function is called after startup.
* The user can use this function to implement the application.
*/
/* USER CODE BEGIN (2) */
#define DMA_CHANNEL_TX DMA_CH1
#define DMA_CHANNEL_RX DMA_CH0
#define MIBSPI1_TX_REQLINE DMA_REQ1
#define MIBSPI1_RX_REQLINE DMA_REQ0
#define TG0_LENGTH 10
uint16 tx_data_mibspi[TG0_LENGTH] = {0xAA01, 0xAA02, 0xAA03, 0xAA04, 0xAA05,0xAA06, 0xAA07, 0xAA08, 0xAA09, 0xAA0A};
uint16 tx_data_mibspi2[TG0_LENGTH] = {0xAB01, 0xAB02, 0xAB03, 0xAB04, 0xAB05,0xAB06, 0xAB07, 0xAB08, 0xAB09, 0xAB0A};
uint16 rx_data_mibspi[TG0_LENGTH + 10];
static g_dmaCTRL g_dmaCTRLPKT_TX,g_dmaCTRLPKT_RX;
void delay(uint32 time)
{
uint32 i = 0;
for(i = 0;i<time;i++);
}
void dmaSetupForMibspi3_Tx(void)
{
g_dmaCTRLPKT_TX.SADD = (uint32)tx_data_mibspi;; /* source address */
g_dmaCTRLPKT_TX.DADD = (uint32)&(mibspiRAM1->tx[0].data);; /* destination address */
g_dmaCTRLPKT_TX.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT_TX.FRCNT = 1 ; /* frame count */
g_dmaCTRLPKT_TX.ELCNT = TG0_LENGTH; /* element count */
g_dmaCTRLPKT_TX.ELDOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT_TX.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_TX.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_TX.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_TX.PORTASGN = PORTA_READ_PORTB_WRITE; /* port b */
g_dmaCTRLPKT_TX.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT_TX.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT_TX.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT_TX.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT_TX.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaCTRLPKT_TX.AUTOINIT = AUTOINIT_OFF; /* autoinit */
dmaSetCtrlPacket(DMA_CHANNEL_TX,g_dmaCTRLPKT_TX); //tx
g_dmaCTRLPKT_RX.SADD = (uint32)&(mibspiRAM1->rx[0].data); /* source address */
g_dmaCTRLPKT_RX.DADD = (uint32)rx_data_mibspi; /* destination address */
g_dmaCTRLPKT_RX.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT_RX.FRCNT = 1; /* frame count */
g_dmaCTRLPKT_RX.ELCNT = TG0_LENGTH; /* element count */
g_dmaCTRLPKT_RX.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_RX.ELSOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT_RX.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_RX.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_RX.PORTASGN = PORTB_READ_PORTA_WRITE;
g_dmaCTRLPKT_RX.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT_RX.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT_RX.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT_RX.ADDMODERD = ADDR_OFFSET; /* address mode read */
g_dmaCTRLPKT_RX.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT_RX.AUTOINIT = AUTOINIT_OFF; /* autoinit */
dmaSetCtrlPacket(DMA_CHANNEL_RX,g_dmaCTRLPKT_RX); //tx
}
void mibspi_DMA_configure(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
{
uint32 bufid = TG0_LENGTH - 1;
uint32 icount = 0;
/* setting transmit and receive channels */
mibspi->DMACTRL[channel] |= (((rxchannel<<4)|txchannel) << 16);
/* enabling transmit and receive dma */
mibspi->DMACTRL[channel] |= 0x8000C000;
/* setting Initial Count of DMA transfers and the buffer utilized for DMA transfer */
mibspi->DMACTRL[channel] |= (icount << 8) |(bufid<<24);
}
/* USER CODE END */
int main(void)
{
/* USER CODE BEGIN (3) */
mibspiInit();
dmaReqAssign(DMA_CHANNEL_TX, MIBSPI1_TX_REQLINE); //DMA request line 4 -- TX (last col, Table 6-41)
dmaReqAssign(DMA_CHANNEL_TX, MIBSPI1_RX_REQLINE); //DMA request line 5 -- RX (last col, Table 6-41)
dmaSetupForMibspi3_Tx();
dmaSetChEnable(DMA_CHANNEL_TX, DMA_SW);
dmaSetChEnable(DMA_CHANNEL_RX, DMA_SW);
mibspi_DMA_configure(mibspiREG1,0,DMA_CHANNEL_TX,DMA_CHANNEL_RX);
dmaEnable();
// mibspiSetData(mibspiREG1, 0, tx_data_mibspi); // to verify without dma
mibspiTransfer(mibspiREG1, 0);
while(!(mibspiIsTransferComplete(mibspiREG1, 0)));
delay(2000);
// mibspiSetData(mibspiREG1, 0, tx_data_mibspi2); // to verify without dma
mibspiTransfer(mibspiREG1, 0);
while(!(mibspiIsTransferComplete(mibspiREG1, 0)));
// mibspiGetData(mibspiREG3, 0, rx_data_mibspi);
while(1);
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
MibSpi1_DMA.zip
