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Original question:

AM263P4-Q1: Multicore usage of one Peripheral (MCAN)

AM263P4-Q1: Different cores with access to same peripheral (ADC,GPIO)

Marcel Pfeifer
Intellectual 355 points

Part Number: AM263P4-Q1
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hey Experts,

ive a systemproject with core 0 and core 1 beeing used. Now i have a signal routed to my ADC0. 
I want to have the signal value at both cores.
So can i read the ADC value with both cores?
TRM says: "In other words, the same ADC result register can be accessed by multiple initiators simultaneously without contention."
But in systemconfig for example i can only asign ADC0 to one core. So its looks to me its not intended by TI to use the same peripheral by different cores.
Or is it a better solution to just use the ADC0 with one core and then send the data over to the other core with IPC?

Best regards

Marcel

  • +1
    Mastermind 9850 points

    The SysConfig is just for that, configuration. Usually the configuration is done only once so it is only assigned to one core.

    However the TRM is saying that you can read the "result register" from multiple cores. You may have to use a different address for the same result register from different cores (I can't remember absolutely) but nonetheless it is still true.

    Marcel Pfeifer said:
    Or is it a better solution to just use the ADC0 with one core and then send the data over to the other core with IPC?

    You could do that too, but not necessary.

  • 0
    TI__Mastermind 25442 points

    Hi Marcel,

    As rightly pointer by Kier, you can do that. Make sure you don't have any MPU settings that would block any core from reading the data. Unless stated in TRM for specific components, the peripherals should be accessible from all cores (for example, some GPIO banks are dedicated to particular R5F cores so you wont be able to directly access them from other core)

    As again shared by Kier, you can use IPC to pass the data around, or you can also have a RAM segment marked as shared memory across cores and dump the data there. You will have to take care of the synchronization to avoid dirty reads and writes since it is a shared data.

    You can refer the IPC Mailbox and Spinlock sections of the TRM and the equivalent examples in the SDK (examples/drives/ipc) if you are interested in using IPC.

    Regards,
    Shaunak