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AM263P4-Q1: Multicore usage of one Peripheral (MCAN)

Marcel Pfeifer
Intellectual 345 points
Part Number: AM263P4-Q1
Other Parts Discussed in Thread: AM263P4

Tool/software:

Hey Experts,

iam working at a SW concept for AM263P4. 
I want to have 2 different softwares. One running on core 0 and one running on core 1.
Is it possible for both to access the same MCAN instance? How can i handle access to that peripheral for different cores?

Best Regards,

Marcel

  • 0
    TI__Mastermind 23773 points

    Hey Marcel,

    This is perfectly acceptable. The MCAN instances are tied to a hard physical address in the SoC Memory Map and any cpu core can obtain access to the CFG/MSG_RAM memory space (assuming the MPU is correctly configured to allow that access). You would call the same API from either core to access the shared MCAN instance.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Intellectual 345 points

    But how to handle the access. I think only one core should initialize the MCAN instance?
    Also what happens if both cores want to write to the MSG_RAM at the same time?
    Is there anything to handle this? Do you maybe have a code example?

    Best Regards,

    Marcel

  • +1 in reply to Marcel Pfeifer
    TI__Mastermind 23773 points

    Hello Marcel,

    Apologies for the delayed response while I was OOO last week. I am not aware of any examples that demonstrate this.

    Correct, only a single core will be responsible for initial configuration of the MCAN instance. Access to the registers can be made my any core that has enabled MPU-configuration for the associated memory region.

    In order to handle access arbitration between multiple cores to MSG_RAM the application should utilize a lock register of the SPINLOCK IP to ensure the previous core has completed its MSG_RAM access before the current core attempts to access the same device resource.

    Additional information can be found in the associated TRM chapter (pg. 833).

    Best Regards,

    Zackary Fleenor