AM2434: CBASS: Arbitration logic to access OCSRAM and DDR4?

AnBer

Part Number: AM2434

Tool/software:

Team,
I saw the below post already: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1515180/am2434-resource-contention-around-cbass

We are looking at more specific information about the internal architecture of the CBASS,
specifically how the arbitration logic is handled for the OCSRAM and DDR4 accesses.

Do we have information that can be made available?

Thanks in advance,
Anthony

10 months ago

0 Stanislav Stilyanov 10 months ago

TI__Mastermind 25070 points

Hi Anthony,

I will check internally with the team.

Thanks,

Stan

0 Christopher Roberts 10 months ago in reply to Stanislav Stilyanov

TI__Genius 10890 points

Anthony,

Can you share specifics around why this information is being requested and how it is intended to be used? The TRM does have some information available, but depending on what specifically you are needing we can determine how best to address.

Thanks,

Chris

0 AnBer 10 months ago in reply to Christopher Roberts

TI__Mastermind 31055 points

Hi Christopher,
Customer need to assess if AM24x could be suited for their end application.
This application has safety requirements like 'Worst-Case Execution Time (WCET)' that must be met.
The internal bus architecture is what connects all together and has direct influence on the WECT.

Thanks in advance,

Anthony

+1 Christopher Roberts 10 months ago in reply to AnBer

TI__Genius 10890 points

Anthony,

I agree bus infrastructure will influence execution time, but I am not quite sure what information can be provided from a design information perspective about bus infrastructure to help the customer predict this behavior. This will be heavily influenced by SW.

We do host an app note about execution benchmarks which have details around access latency. Maybe this is a better source document to help the customer gauge performance??

https://www.ti.com/lit/pdf/spracv1

Let me know what questions may remain after reviewing this document and if there is something more specific about what information is needed to support.

Thanks,

Chris

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AM2434: CBASS: Arbitration logic to access OCSRAM and DDR4?