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MSPM0G1519: Cascading DMAs Trigger - Laterncy and Timing

Philip Neaves
Intellectual 340 points

Part Number: MSPM0G1519

Hello.

I am doing pattern generation to GPIOs with DMA; works good.

I have two DMAs; each triggered by the other.

DMA1 is first triggered in software and once started both DMAs are set to be triggered by the other DMA...it will go on for ever (which is what I want).

DMA1 Sofware trigger-> DMA2 -> DMA1 -> DMA2 -> DMA1....

I have this from Eason Zhou

DMA.pdf 

But this is for a software trigger; there must be additional latency for the ending of fitst DMA to start next DMA ?

Thanks

 

 

  • 0
    TI__Mastermind 27765 points

    Hi Philip,

    For my understanding, the 6 cyles latency is introduced with 2 parts, software latency and hardware latency.

    And for the subsequent transfer, there only has the hardware latency, as no further software trigger required.

    So, it will be 3 cycles with the files you shared here.

    B.R.

    Sal