Original question:
Hello,
I have following queries on ECC module. Please reply to these questions.
Hi Deviprasad,
Apologies for the delayed response!
- Will the ECC bits are enabled by RBL development boot mode(debug)?
- What is the behavior when ECC fails when RBL is running?
RBL code doesn't have ECC validations.
During a data abort exception, how can one differentiate between a double-bit error and an inject-only mode trigger?
Typically, ECC error injection is not enabled continuously. It is a controlled test mechanism that runs for only a few microseconds. During error-injection, the software explicitly programs corresponding ECCCTRL (or equivalent ECC control) registers to force an artificial single-bit or double-bit errors.
Because the software initiates the injection at a known time and has full control over the sequence, injected errors can be easily distinguished from real, spontaneous ECC errors. Outside the injection window, the ECC logic operates normally and detects only genuine memory faults.
Which status flag will get set when 2bit ECC error is injected in TCM memory?
It is 0x2F (47) and 0x30 (48).
47th bit for single-bit error and 48th bit for double-bit errors.
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Thanks & regards,
Jagadish.
