AM2432: FLASH part BOOT mode selection

Hello Vaibhav,

Thank you for your query !

Are you going to boot an RTOS, Linux or some bare metal application ?

What are the requirements (execute in place, read to DRAM, speed )  for the initial stage when AM2432 ROM loader booting your first bootloader ?

Similarly, what are the requirements for the next boot stages (custom bootloader, standard bootloaders, OS kernels, apps ) ?

Thanks

Kind Regards,

Anastas Yordanov 

HI Anastas, 

Thanks for response, 

Below is answer to your question. 

Anastas Yordanov said:

Are you going to boot an RTOS, Linux or some bare metal application ?

--> Will use RTOS base application firmware, 

Anastas Yordanov said:

What are the requirements (execute in place, read to DRAM, speed )  for the initial stage when AM2432 ROM loader booting your first bootloader ?

----> We are not using the external DRAM, Let me know does this is answer to your question or not?

Anastas Yordanov said:

Similarly, what are the requirements for the next boot stages (custom bootloader, standard bootloaders, OS kernels, apps ) ?

--> As per my understanding, we go with Standard Bootloader in OSPI mode. 

Let me know if you have any further questions or above point not satisfactory answer to your question?

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Best Regards, 

Vaibhav 

Hi Vaibhav,

Thank you for the update. I have some other questions.

VK said:

----> We are not using the external DRAM, Let me know does this is answer to your question or not?

So I understand you are not going to load image to an external DDR. So in ROM boot stage, do you intend to execute the SBL (secondary bootloader) from the SoC OCM-RAM (on chip SRAM) or to use XiP feature of the NOR Flash IS25WX064 ?

Any preferred configuration of the OSPI boot modes (considering speed, protocol complexity, etc.) ?

What do you mean under standard bootloader ?

Thanks

Kind Regards,

Anastas

Hi Anastas,

Thanks for your quick feedback,

Our simple target is to run the board after the Power ON cycle and execute the program that will be stored in IS25WX064 OSPI FLASH. We will set the OSPI as boot mode on the boot step pin.

Could you please provide the exact steps and parameters that need to be set? I am not a firmware expert, so I will follow your guidance.

Vaibhav

Anastas Yordanov said:

So I understand you are not going to load image to an external DDR. So in ROM boot stage, do you intend to execute the SBL (secondary bootloader) from the SoC OCM-RAM (on chip SRAM) or to use XiP feature of the NOR Flash IS25WX064 ?

We do not have any requirement for the SBL to execute in SoC OCM-RAM or to utilize the XiP feature of the NOR Flash IS25WX064. We are fine with the simplest method that ensures the board is operational.

Anastas Yordanov said:

Any preferred configuration of the OSPI boot modes (considering speed, protocol complexity, etc.) ?

No any prefernce,

Let me know if you need any feedback from my side?

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Vaibhav

Hello Vaibhav,

Thank you for clarifying.

In the meantime you may want to also refer to this E2E thread that contains useful resources regarding OSPI modes of operation / clocking speeds:

Resources rgd AM64x/AM243x OSPI modes of operation with NOR flash

Please expect my feedback by EOB today or tomorrow.

Thanks

Kind Regards

Anastas Yordanov

Hi Anastas, 

Thanks for sharing details with us. 

Just for your reference we are planning to supply 1.8V to the OSPI FLASH memory. 

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Vaibhav

Hello Vaibhav,

Thanks for providing your OSPI HW interface related schematic !

I will follow-up shortly with analysis on the possible OSPI related boot configurations with the IS25WX064-JHLE NOR flash.

Kind Regards,

Anastas Yordanov 

Hello Vaibhav,

For an OSPI boot mode:

Considering a DQS line connectivity between the AM243x processor OSPI host and your IS25WX064-JHLE Flash memory, I would recommend the following AM243x ROM boot sub-mode (highlighted in green):

You can find the above information on Bootmode pin states and the OSPI interface ROM code-expected configurations in the Chapter, Initialization / Section, Boot Modes / Section: OSPI, xSPI, QSPI, SPI Boot of the AM243x TRM.

Note that the maximal achieved OSPI0_CLK frequency supported by the ROM code for this sub-mode (DQS connectivity) is 50 MHz. Within a Non-ROM Bootloader (i.e. within your standard or custom bootloader) however you will be able to switch to higher boot speeds because the DQS connection in OSPI host PHY mode allows for higher OSPI memory transfer speeds. 

To select the above OSPI boot mode, the boot mode selection pin  BOOTMODE8 shall be set to 0b1 (to ensure that LBCLKO is a no connect and internal ), BOOTMODE7 pin shall be set to 0b0 or 0b1 according to the OSPI0 CSn (where n=0 or 1) to which you attach the Flash memory.  For this mode it is important that the AM243x LBCLKO pin must be NO connect, meaning without a PCB trace connected to it.

Let me know if you plan to simultaneously use the OSPI boot mode  and mux any other interface on the LBCLKO pin. I will need to clarify if this would be possible at all. While in OSPI boot mode, the AM243x ROM loader will boot in a PHY SDR: 1S-1S-8S OSPI configuration. My understanding is that during the ROM boot stage (PHY SDR mode @ 50MHz) the DQS signal is not used. If DQS signal used during next stage boots, an OSPI PHY DDR configuration shall be chosen.

Please find more information on ROM loader behavior in the OSPI Boot mode in the sub-sections of the Chapter, Initialization /  Section, Boot Modes / Section, OSPI Boot of the AM243x TRM.

For the full boot mode pin value configurations BOOTMODE0-BOOTMODE15 to select any of my suggested AM243x ROM boot modes you can refer to the Chapter, Initialization /  Section, Boot Mode Pins of the AM243x TRM.

For an xSPI boot mode: 

Let's look at the below table in Chapter, Initialization /  Section, Boot Modes / Section, xSPI Boot of the AM243x TRM.:

I found out that the ROM supported command 0xEE for a fast read in 8D-8D-8D is not available in the IS25WX064-JHLE documentation, therefore it is unsupported by this flash memory.  This means that a xSPI boot with  BOOTMODE9=0b0, BOOTMODE8=0b1, BOOTMODE7=0b1 is unsupported by the Flash memory.

A xSPI boot with  BOOTMODE9=0b0, BOOTMODE8=0b0, BOOTMODE7=0b0 is supported by the Flash memory in 1S-1S-1S at OSPI0_CLK freq= 50 MHz

Both the AM243x ROM and  IS25WX064-JHLE flash memory are SFDP compatible, meaning they both support the SFDP feature as per JEDEC JESD216. So with BOOTMODE9=0b1, BOOTMODE8 = don't care, BOTMODE7=don't care you can achieve a ROM xSPI boot that starts in traditional SPI boot mode: 1S-1S-1S at OSPI0_CLK freq= 50 MHz  and a subsequent switch via SFDP header learned command to a DDR 8D-8D-8D booting but with ROM limited OSPI_CLK freq = 25 MHz. 

Last but not least, for your IS25WX064-JHLE Flash memory the XiP (execute-in-place) feature is supported in the xSPI operation mode of the memory.

Le me know If you need to execute a bootloader fro FLASH during AM243x ROM boot, I need a confirmation from an AM243x ROM expert if the XiP enable/operation commands specific for the IS25WX064-JHLE are supported by the ROM bootloader.

I understand that enabling of xSPI mode for IS25WX064-JHLE can allow XiP execution of code from the OSPI Flash memory (instead of load to RAM and execution from RAM). So the appropriate XIP commands can be also applied in any of the next stage bootloaders. For more information on enabling XIP feature in AM243x SDK please refer to this thread: AM243x XIP mode enabling

I hope this helps you find the solution.

Thanks

Kind Regards,

Anastas Yordanov

Hi Anastas, 

Thanks for your detailed explanation. We always appreciate your support.

Anastas Yordanov said:

For this mode it is important that the AM243x LBCLKO pin must be NO connect, meaning without a PCB trace connected to it.

For future expansion or test, We have just 3mm long trace on the LBCLKO pin, will it work or we need to remove it.

I assume that you have checked the IS25WX064-JHLE memory support the boot in OSPI boot mode (kindly confirm the same) , So we move ahead with OSPI boot mode.

in case XIP feature needed (due to any limitation of on-chip-RAM of AM2432) than we move back to xSIP. 

Thanks again for your support

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Best Regards,

Vaibhav

Hello Vaibhav,

I understand that the availability of a 3 mm long trace for a  series termination resistor on the AM243x OSPI0_LBCLKO pin is NOT a problem. You just do NOT use any series resistor to keep the LBCLKO unconnected. Please refer to the: Schematic Design Guidelines and Schematic Review checklist for AM243x/AM64x regarding the LBCLKO and other AM243x OSPI pin schematic / layout recommendations.

You also make sure to use this AM243x Datasheet  DQS clocking topology and layout recommendation to flawlessly achieve higher speeds of OSPI operations:

VK said:

I assume that you have checked the IS25WX064-JHLE memory support the boot in OSPI boot mode (kindly confirm the same) , So we move ahead with OSPI boot mode.

It seems that the AM263Px ROM OSPI Boot mode is used and therefore tested by TI with the IS25WX064 similar IS25LX256-LHLE NOR Flash memory on the AM263P-LP EVM. Regarding the differencies between the two flash memories, kindly refer again to the E2E thread that you attached: RE: AM2432: OSPI Read/Write Isse with the custom flash - IS25WX064  You can check that OSPI Boot Mode is supported by the IS25LX256-LHLE in the below highlighted pages of the AM263P MCU+ SDK documentation - AM263Px MCU+ SDK: EVM Setup.

Unfortunately I do NOT have a custom AM243x board with an IS25WX064-JHLE NOR Flash memory on it and have NOT tested ROM booting SBL or other bootloader software booting apps from this Flash memory. So far I haven't found a confirmation in the E2E forum that such a configuration has already been tested.

For some reason, the AM263P MCU+ SDK documentation does NOT cover the xSPI boot mode which is essentially supported by the IS25WX064-JHLE NOR Flash and also by the AM263P ROM loader. Generally the xSPI mode is tested on AM243x EVM (but with a different Flash memory - S28HS512T) to have achieved the best OSPI to Flash  read transfer clock frequency (up to 166 MHz) in the xSPI 8D-8D-8D. To make such speeds possible, the OSPI PHY DDR mode shall be used and a DQS input from Flash memory to the AM243x. (I understand DQS not  used by the ROM boot @ 50MHz in PHY SDR 1S-1S-8S mode - in this case only internal PHY loopback used as a ref. clock feedback).   

Let me know if you have further questions ?

Thanks

Kind Regards,

Anastas Yordanov