AM2434: Do registers read latency improve

Bolt Hsieh

Part Number: AM2434
Other Parts Discussed in Thread: TMS320F28386D,

Hi experts,

With reference to the two topics :

AM2434: If any possible, reduce FSI registers read/write latency - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

AM2434: Do registers read latency improve in MCU+ SDK 09.01.00 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

May I ask from which SDK version or compiler version and above the read/write operations of registers on the R5F and PRU can effectively reduce access time? Additionally, what are the actual reduction figures?

We are currently using the following method for register read/write operations. Is this method also effective?

Reg. Operate	R5F	PRU( C code )
Read	HW_RD_REG16( )	HW_RD_REG16( )
Write	HW_WR_REG16( )	HW_WR_REG16( )

Best Regards

Bolt

5 months ago

0 Nick Saulnier 5 months ago

TI__Guru** 109630 points

Hello Bolt,

This thread is currently assigned to a different team member who will be commenting from the R5F/MCU+ side. I will be commenting from the PRU side.

PRU Read/Write latencies

What is your usecase?

The PRU C compiler has the option to play around with optimization (more optimization often leads to more efficient code, but the compiler is also more likely to move around some of the instruction execution in a way that you don't expect. The generated assembly instructions will still do exactly what you programmed in C, but the order is less likely to be the way a human reader would expect).

If this is a time-sensitive operation, I typically suggest programming directly in assembly, since that allows you to control exactly what the PRU core is doing at every single clock cycle. It is also pretty common for customers to write code in C, and then program their timing-sensitive functions in assembly.

For more information about PRU read/write latencies,

please refer to
[FAQ] PRU: How do I calculate read and write latencies?

The team and I are writing tests to re-validate all the information, which will eventually be published to the new OpenPRU repo. Then we will refresh the old PRU Read Latencies app note in 2026.

Future readers, feel free to create a new e2e thread to ask us for an update.

For more information about getting started with PRU development on AM243x,

Please refer to the AM243x academy's new PRU module.

The PRU Academy is still being actively written. I am the lead author. If you have questions or feedback, please create a separate e2e thread and it will make its way back to me.

Regards,

Nick

0 Nick Saulnier 5 months ago in reply to Nick Saulnier

TI__Guru** 109630 points

For future readers, Bolt has created several related e2e threads. We will probably try to keep this e2e thread focused on R5F cores reading & writing, and discuss detailed PRU concepts on the other threads:

PRU C code vs assembly code:
AM2434: PRU - C code application suggest

More information about PRU's XFR2VBUS
AM2434: PRU application - XFR2VBUS Optimization

Regards,

Nick

0 Bolt Hsieh 5 months ago in reply to Nick Saulnier

Prodigy 185 points

Hello Nick,

Thank you for your response.

Regarding the PRU portion, I will continue following the updates in the other threads.

For this thread, I will continue to wait for the explanation on optimizing the R5F register read/write latency.

Best Regards
Bolt

0 Bolt Hsieh 5 months ago in reply to Bolt Hsieh

Prodigy 185 points

Hi Nick,

Excuse me, could you please help to check when we can expect a response or any related information regarding the R5F register read/write latency improvement?

Best Regards
Bolt

0 Bolt Hsieh 4 months ago in reply to Bolt Hsieh

Prodigy 185 points

Hi experts,

Regarding the R5F register read/write latency improvement, do you have any suggestions or updates?

Best Regards
Bolt

0 Rich Chen 4 months ago in reply to Bolt Hsieh

TI__Expert 4440 points

Swargam,

This is TI EP FAE in filed.

This e2e post regarding to register read/write latency including R5F and PRU two portions.

Nick has replied PRU portion and currently need your help to comment on R5F portion.

New MCU SDK seems improve register read/write latency and we expect to get team's insight on how can customer reduce read/write latency on FSI registers access.

May you advise the improvement on SDK 9.02?

BR, Rich

0 Rich Chen 4 months ago in reply to Rich Chen

TI__Expert 4440 points

Swargam,

Is this part of MCU SDK?

May you comment on R5F portion?

BR, Rich

0 Tushar Thakur 4 months ago

TI__Guru 61408 points

Hello

Bolt Hsieh said:
We are currently using the following method for register read/write operations. Is this method also effective?

The function mentioned in the above table performs direct read/write from the memory address.

Please refer image below.

Rich Chen said:
New MCU SDK seems improve register read/write latency and we expect to get team's insight on how can customer reduce read/write latency on FSI registers access.

What latency numbers are the customer getting? What is the requirement here?

In which profile are they building example? Is it release or debug?

What optimization levels are being used?

Regards,

Tushar

0 Bolt Hsieh 4 months ago in reply to Tushar Thakur

Prodigy 185 points

Hi Tushar,

Thank you for your response.

The underlying implementation of the HW_RD_REG16() and HW_WR_REG16() functions is currently the same as the approach you described.

Tushar Thakur said:
What latency numbers are the customer getting? What is the requirement here?

Regarding this topic, please refer to the previous discussion thread - AM2434: If any possible, reduce FSI registers read/write latency - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums. I have included a screenshot below for reference. Our main objective is to align the read/write latency with that of the F28386.

Instruction latency \ Processor	TMS320F28386D CPU	AM2434 CPU	AM2434 PRU
Read latency per register (us)	0.02	0.09	0.33
Write latency per register (us)	0.01	0.01	0.02

Additionally, in the previous discussion thread- AM2434: Do registers read latency improve in MCU+ SDK 09.01.00 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums it was mentioned that updating the SDK to version 9.1 or later would improve the read/write latency(as below figure). Could you please confirm whether this statement is accurate? If there is an improvement, could you also share the quantitative data or figures regarding the latency reduction?

Tushar Thakur said:
In which profile are they building example? Is it release or debug?

What optimization levels are being used?

Regarding this topic as well, please refer to the earlier discussion thread - AM2434: Q. AM2434 Compiler and Optimization Settings for Higher Execution Efficiency - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums. Our current configuration is based on a release build, and the R5F optimization setting is set to "s". If you have any recommendations specifically targeting read/write latency optimization, we would appreciate it if you could also provide the corresponding compiler configuration settings.

Best Regards
Bolt

0 Vaibhav Kumar 4 months ago in reply to Bolt Hsieh

TI__Guru 56684 points

Hi,

The assigned expert is out of office, please expect delayed responses.

Regards,

Vaibhav

0 Tushar Thakur 4 months ago in reply to Bolt Hsieh

TI__Guru 61408 points

Hi Bolt,

Bolt Hsieh said:
Read latency per register (us) 0.02 0.09 0.33

Which register is being read here?

Is this located in the MAIN domain or MCU domain? From which core this is being read?

At what frequency the core are running?

I can see the table which you shared above compares two different CPU architecture. (C2000 and AM243x).

Regards,

Tushar

0 Bolt Hsieh 3 months ago in reply to Tushar Thakur

Prodigy 185 points

Hi Tushar,
I apologize for the delayed response.

Tushar Thakur said:
Which register is being read here?

FSI register read/write, you can reference - AM2434: If any possible, reduce FSI registers read/write latency - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Tushar Thakur said:
Is this located in the MAIN domain or MCU domain?

FSI module is in the Main domain.

Tushar Thakur said:
From which core this is being read?

AM24x- CPU : R5F0_0
AM24x- PRU : PRU-ICSSG0 - PRU0 - PRU
F28386 - CPU1

Tushar Thakur said:
At what frequency the core are running?

AM24x- CPU : 800MHz
AM24x- PRU : 333MHz
F28386 - CPU1 : 200MHz

Best Regards
Bolt

0 Tushar Thakur 3 months ago in reply to Bolt Hsieh

TI__Guru 61408 points

Hi Bolt,

I tried with AM64x MCU+SDK v11.02 and my code took Average 0.11us to read the TX_FRAME_CTRL and RX_FRAME_INFO register of FSI0 Module.

The R5F core is running at 800 MHz and the function to read the above register is kept in TCMA memory.

The numbers are taken with release build of the project. I don't see a 0.9us read latency. Please let us know if a specific register needs to be read.

Regards,

Tushar

0 Bolt Hsieh 3 months ago in reply to Tushar Thakur

Prodigy 185 points

Hi Tushar,

With reference to AM2434: If any possible, reduce FSI registers read/write latency - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

The description of reading from and writing to the FSI module is as follows.

Instruction latency \ Processor	TMS320F28386D CPU	AM2434 CPU	AM2434 PRU
Read latency per register (us)	0.02	0.09	0.33
Write latency per register (us)	0.01	0.01	0.02

The measured read time is 0.09 µs, not 0.9 µs as previously you mentioned. Our expectation is to reduce this to approximately 0.02 µs.

However, based on the test data you provided, the measured value is 0.11 µs, which seems to indicate that the newer SDK does not improve the read/write latency. Is this understanding correct?

If so, may we ask why there was earlier information( AM2434: Do registers read latency improve in MCU+ SDK 09.01.00 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums ) indicating that SDK version 9.02 or later would provide improvements in read/write latency? Does this mean that the corresponding optimization item has not yet been implemented, or is it related to a different improvement scope?

Thank you for your clarification and support.

Best Regards
Bolt

+1 Tushar Thakur 3 months ago in reply to Bolt Hsieh

TI__Guru 61408 points

Hi Bolt,

Bolt Hsieh said:
The measured read time is 0.09 µs, not 0.9 µs as previously you mentioned. Our expectation is to reduce this to approximately 0.02 µs.

Thanks for correcting me.

Bolt Hsieh said:
Is this understanding correct?

Yes, this is correct. I have checked the Jira status. The Jira is closed because it is limitation on hardware side and the latency cannot be reduced via software improvements.

Regards,

Tushar