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Original question:

AM2434: If any possible, reduce FSI registers read/write latency

AM2434: Do registers read latency improve

Bolt Hsieh
Prodigy 165 points
Part Number: AM2434


Hi experts,

With reference to the two topics :

AM2434: If any possible, reduce FSI registers read/write latency - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

AM2434: Do registers read latency improve in MCU+ SDK 09.01.00 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

May I ask from which SDK version or compiler version and above the read/write operations of registers on the R5F and PRU can effectively reduce access time? Additionally, what are the actual reduction figures? 

We are currently using the following method for register read/write operations. Is this method also effective?

Reg. Operate R5F PRU( C code )
Read HW_RD_REG16( ) HW_RD_REG16( )
Write HW_WR_REG16( ) HW_WR_REG16( )

Best Regards

Bolt

  • 0
    TI__Guru** 106230 points

    Hello Bolt,

    This thread is currently assigned to a different team member who will be commenting from the R5F/MCU+ side. I will be commenting from the PRU side.

    PRU Read/Write latencies

    What is your usecase?

    The PRU C compiler has the option to play around with optimization (more optimization often leads to more efficient code, but the compiler is also more likely to move around some of the instruction execution in a way that you don't expect. The generated assembly instructions will still do exactly what you programmed in C, but the order is less likely to be the way a human reader would expect).

    If this is a time-sensitive operation, I typically suggest programming directly in assembly, since that allows you to control exactly what the PRU core is doing at every single clock cycle. It is also pretty common for customers to write code in C, and then program their timing-sensitive functions in assembly.

    For more information about PRU read/write latencies,

    please refer to 
    [FAQ] PRU: How do I calculate read and write latencies?

    The team and I are writing tests to re-validate all the information, which will eventually be published to the new OpenPRU repo. Then we will refresh the old PRU Read Latencies app note in 2026.

    Future readers, feel free to create a new e2e thread to ask us for an update.

    For more information about getting started with PRU development on AM243x,

    Please refer to the AM243x academy's new PRU module.

    The PRU Academy is still being actively written. I am the lead author. If you have questions or feedback, please create a separate e2e thread and it will make its way back to me.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Guru** 106230 points

    For future readers, Bolt has created several related e2e threads. We will probably try to keep this e2e thread focused on R5F cores reading & writing, and discuss detailed PRU concepts on the other threads:

    PRU C code vs assembly code:
    AM2434: PRU - C code application suggest

    More information about PRU's XFR2VBUS
    AM2434: PRU application - XFR2VBUS Optimization

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 165 points

    Hello Nick,

    Thank you for your response.

    Regarding the PRU portion, I will continue following the updates in the other threads.

    For this thread, I will continue to wait for the explanation on optimizing the R5F register read/write latency.

    Best Regards
    Bolt

  • 0 in reply to Bolt Hsieh
    Prodigy 165 points

    Hi Nick,

    Excuse me, could you please help to check when we can expect a response or any related information regarding the R5F register read/write latency improvement?

    Best Regards
    Bolt

  • 0 in reply to Bolt Hsieh
    Prodigy 165 points

    Hi experts,

    Regarding the R5F register read/write latency improvement, do you have any suggestions or updates?

    Best Regards
    Bolt

  • 0 in reply to Bolt Hsieh
    TI__Expert 4380 points

    Swargam, 

    This is TI EP FAE in filed. 

    This e2e post regarding to register read/write latency including R5F and PRU two portions. 

    Nick has replied PRU portion and currently need your help to comment on R5F portion. 

    New MCU SDK seems improve register read/write latency and we expect to get team's insight on how can customer reduce read/write latency on FSI registers access. 

    May you advise the improvement on SDK 9.02? 

    BR, Rich

  • 0 in reply to Rich Chen
    TI__Expert 4380 points

    Swargam, 

    Is this part of MCU SDK?

    May you comment on R5F portion? 

    BR, Rich

  • 0
    TI__Guru 55498 points

    Hello

    Bolt Hsieh said:
    We are currently using the following method for register read/write operations. Is this method also effective?

    The function mentioned in the above table performs direct read/write from the memory address.

    Please refer image below.

    Rich Chen said:
    New MCU SDK seems improve register read/write latency and we expect to get team's insight on how can customer reduce read/write latency on FSI registers access.

    What latency numbers are the customer getting? What is the requirement here?

    In which profile are they building example? Is it release or debug?

    What optimization levels are being used?

    Regards,

    Tushar