AM2634: Query on AM2634

1. Does communication halts at 100KHz as well? Or this is observed only at 400KHz?

    If possible, please share your board schematic details.

    Few points to consider during board design:

•  Proper pull-up resistors
•  Keep I2C traces short and parallel for operation at higher speed

2. Can you please share which specific register (Provide name as per AM2634 register addendum) you are talking about here?

3. Spanning Tree Protocol is supported by CPSW in AM2634. Currently we do not have any example supporting STP.

4.  EQEP modules typically do not provide separate counters for individual A and B channels. Instead, it interprets the relative phase relationship between channels A and B to determine direction (clockwise or counterclockwise) and counts accordingly in a single position counter.

     There are 3 instances of EQEP supported in AM2634

5. 2MB for flash size limitation on flash is not a hard physical limit of the external flash itself, but rather due to max size of On-Chip RAM being 2MB. AM2634 device does not execute directly from flash. And standard bootloaders (SBL) for this device copy the application image from external flash into the internal 2MB OCRAM or TCM before execution. Hence the limitation on flash size.

1) I2c communication never halts at 100 khz.It is observed only with 400 khz, we have used 1.5k and 4.7k resistors as pull up but we faced issue with I2C
2) UART_LSR_UART

For I2C failure at 400Khz:

1. Can you please share waveforms of transaction failures?

2. Does master acknowledge above transaction? Where does transaction fails exactly?

3. What voltages are seen on SDA and SCL lines?

4. If possible, please share board schematic as well.

UART: UART_LSR register:

TX_EMPTY_CTRL_IT bit in UART_SCR register can be used to generate interrupt when FIFO is empty.

This is same as UART_LSR bit 6.

6835.I2C.docx

Please find our observations and wave forms in the attached word file regarding the I2C

Couple of suggestion you can try:

1. The non-sharp rising edges you observe indicate RC time constant issues with your pull-up, and also 1.5K show improvement in waveforms, can you use 1KΩ/680Ω register instead of 4.7KΩ/1.5KΩ

2. Can you please elaborate need for using Isolator between two controllers, as it can introduce timing delay/signal distortion. Is it possible to remove this isolator?

3.  The target device is likely holding the clock line low (clock stretching) because it needs more time to process data or prepare a response. At 400 KHz, the target may not be able to keep up with the faster clock rate. Can you Insert small delays between transactions to give the slave more processing time?

Requirement of Isolated I2C: Our system need to communicate with adjacent system through I2C the sources are not same we don't want to make both systems ground common that's why we used isolated I2C which gets powered by Isolated supply we combined the grounds of two isolated sources of the systems.

Can you please run with lower resistor value, as suggested above?

If lowering resistor value does not help, potential reason is target not be able to keep up with the faster clock rate and master is looses arbitration when attempting to initiate a transfer while BB=1.

To confirm this, please poll for AL(Arbitration Lost) flag in ICSTR register. If this is set and MST bit is 0--> I2C becomes a slave.

In that case, please clear this flag as by writing '1' to it or by reading ICIVR(001). Also clear BB bit in ICSTR and initiate a new transfer.