Part Number: TMS570LC4357-EP
Other Parts Discussed in Thread: LAUNCHXL2-570LC43, HALCOGEN, , TMS570LC4357
Hai Team,
I am using TMS570LC4357-EP controller with the LAUNCHXL2-570LC43(B) development kit, In this I have intialized the SCI1 and SCI2 in the halcogen with 9600bps buadrate, 2 stop bits and no parity. The Rx interrupt was enabled, I am trying to send some 32 bytes of data in signle frame and monitroing at the terminal end using docklight. But the issue is the transmit is not occured and the DMA interrupt is not occured. I have shared the test code for refernece. Kindly do the needful.
#include "HL_sys_common.h"
#include "HL_sci.h"
#include "HL_sys_dma.h"
#include "HL_sys_vim.h"
#include "HL_system.h"
/* DMA Request Assignments for TMS570LC4357 */
/* SCI DMA Enable Bits */
#define SCI_SET_TX_DMA (1<<16)
#define SCI_SET_RX_DMA (1<<17)
#define SCI_SET_RX_DMA_ALL (1<<18)
/* Buffer Size */
#define BUFFER_SIZE 32
/* Buffers - Must be in shared RAM */
#pragma DATA_SECTION(TX_DATA, ".sharedRAM")
#pragma DATA_SECTION(RX_DATA, ".sharedRAM")
uint8 TX_DATA[BUFFER_SIZE];
uint8 RX_DATA[BUFFER_SIZE];
g_dmaCTRL g_dmaCTRLPKT1, g_dmaCTRLPKT2;
/* SCI Register Addresses - Handle endianness */
#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
#define SCI2_TX_ADDR ((uint32)(&(sciREG2->TD)))
#define SCI2_RX_ADDR ((uint32)(&(sciREG2->RD)))
#else
#define SCI1_TX_ADDR ((uint32)(&(sciREG1->TD)) + 3)
#define SCI1_RX_ADDR ((uint32)(&(sciREG1->RD)) + 3)
#define SCI2_TX_ADDR ((uint32)(&(sciREG2->TD))+3)
#define SCI2_RX_ADDR ((uint32)(&(sciREG2->RD))+3)
#endif
int main(void)
{
uint32 sciTxData, sciRxData;
int i;
/* Load test data */
for (i = 0; i < BUFFER_SIZE; i++)
{
TX_DATA[i] = i;
}
/* Initialize SCI */
sciInit();
/* Enable DMA */
dmaEnable();
#if 0
/* Assign DMA request SCI1 TX to Channel 0 */
dmaReqAssign(DMA_CH0, DMA_REQ29);
/* Assign DMA request SCI1 RX to Channel 1 */
dmaReqAssign(DMA_CH1, DMA_REQ28);
sciTxData = SCI1_TX_ADDR;
sciRxData = SCI1_RX_ADDR;
#else
/* Assign DMA request SCI2 TX to Channel 0 */
dmaReqAssign(DMA_CH0, DMA_REQ41);
/* Assign DMA request SCI2 RX to Channel 1 */
dmaReqAssign(DMA_CH1, DMA_REQ40);
sciTxData = SCI2_TX_ADDR;
sciRxData = SCI2_RX_ADDR;
#endif
/* Configure DMA Control Packet for TX (Channel 0) */
g_dmaCTRLPKT1.SADD = (uint32)TX_DATA;
g_dmaCTRLPKT1.DADD = sciTxData;
g_dmaCTRLPKT1.CHCTRL = 0;
g_dmaCTRLPKT1.FRCNT = 1;
g_dmaCTRLPKT1.ELCNT = BUFFER_SIZE;
g_dmaCTRLPKT1.ELDOFFSET = 0;
g_dmaCTRLPKT1.ELSOFFSET = 1;
g_dmaCTRLPKT1.FRDOFFSET = 0;
g_dmaCTRLPKT1.FRSOFFSET = 0;
g_dmaCTRLPKT1.PORTASGN = PORTB_READ_PORTB_WRITE;
g_dmaCTRLPKT1.RDSIZE = ACCESS_8_BIT;
g_dmaCTRLPKT1.WRSIZE = ACCESS_8_BIT;
g_dmaCTRLPKT1.TTYPE = FRAME_TRANSFER;
g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1;
g_dmaCTRLPKT1.ADDMODEWR = ADDR_FIXED;
g_dmaCTRLPKT1.AUTOINIT = AUTOINIT_OFF;
/* Configure DMA Control Packet for RX (Channel 1) */
g_dmaCTRLPKT2.SADD = sciRxData;
g_dmaCTRLPKT2.DADD = (uint32)RX_DATA;
g_dmaCTRLPKT2.CHCTRL = 0;
g_dmaCTRLPKT2.FRCNT = 1;
g_dmaCTRLPKT2.ELCNT = BUFFER_SIZE;
g_dmaCTRLPKT2.ELDOFFSET = 1;
g_dmaCTRLPKT2.ELSOFFSET = 0;
g_dmaCTRLPKT2.FRDOFFSET = 0;
g_dmaCTRLPKT2.FRSOFFSET = 0;
g_dmaCTRLPKT2.PORTASGN = PORTB_READ_PORTB_WRITE;
g_dmaCTRLPKT2.RDSIZE = ACCESS_8_BIT;
g_dmaCTRLPKT2.WRSIZE = ACCESS_8_BIT;
g_dmaCTRLPKT2.TTYPE = FRAME_TRANSFER;
g_dmaCTRLPKT2.ADDMODERD = ADDR_FIXED;
g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1;
g_dmaCTRLPKT2.AUTOINIT = AUTOINIT_OFF;
/* Set control packets */
dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT1);
dmaSetCtrlPacket(DMA_CH1, g_dmaCTRLPKT2);
/* Enable DMA channels */
dmaSetChEnable(DMA_CH0, DMA_HW);
dmaSetChEnable(DMA_CH1, DMA_HW);
#if 0
/* Enable SCI DMA requests */
// sciREG1->SETINT |= SCI_SET_TX_DMA | SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;
sciREG1->SETINT |= SCI_SET_TX_DMA;
#else
/* Enable SCI DMA requests */
sciREG2->SETINT |= SCI_SET_TX_DMA | SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;
#endif
/* Wait for DMA transfer complete */
while (!dmaGetInterruptStatus(DMA_CH1, BTC));
/* Disable DMA channels */
dmaSetChEnable(DMA_CH0, DMA_SW);
dmaSetChEnable(DMA_CH1, DMA_SW);
/* Verify received data */
for (i = 0; i < BUFFER_SIZE; i++)
{
if (RX_DATA[i] != TX_DATA[i])
{
/* Data mismatch - handle error */
while(1); // Stop here for debugging
}
}
/* If we reach here, DMA transfer was successful */
while(1)
{
/* Application code */
}
return 0;
}
MEMORY
{
VECTORS (X) : origin=0x00000000 length=0x00000020
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200000 length=0x00200000
STACKS (RW) : origin=0x08000000 length=0x00001500 /* 5.25 KB */
SHAREDRAM (RW) : origin=0x08001500 length=0x00000400 /* 1 KB for DMA */
RAM (RW) : origin=0x08001900 length=0x0007E700 /* Remaining ~506 KB */
}
SECTIONS
{
.intvecs : {} > VECTORS
.text : {} > FLASH0
.const : {} > FLASH0
.cinit : {} > FLASH0
.pinit : {} > FLASH0
.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM
.sharedRAM : {} > SHAREDRAM /* DMA buffers */
}
