Part Number: MSPM0G3507
Dear TI Forum,
I am referring to the document: Functional Safety Manual for MSPM0G3x0x-Q1(SFFS624B – MARCH 2024 – REVISED AUGUST 2025), and to Section 5.5 CPU.
The following is stated: "Prefetch logic to improve sequential code execution, and I-cache with four 64-bit cache lines".
Is this prefetch and cache also used to fetch data (like constants, fixed pointers, etc) faster from the flash (so not just instructions)?
Thank you in advance for the clarification!
