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TMS570LC4357-EP: EMIF performance: max VLCK3 frequency for Async and sync mode?

AnBer
Mastermind 30625 points

Part Number: TMS570LC4357-EP

Team,
Can you please confirm which one of the below two posts is correct?

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/905741/tms570lc4357-emif-performance-for-sram
mentions that the max VCLK3 for both Sync and Async interface is 100Mhz

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/594509/tms570lc4357-emif-clock-for-asynchronous-access
mentions that max VCLK3 is 150Mhz for Sync interface and is 100Mhz for async interface.

What is the correct information?
Thanks in advance for confirming!

Anber

 

 

  • 0
    TI__Guru* 75156 points

    Hi Anber,

    According to the datasheet EMIF section the min possible EMIF_CLK is mentioned as 10ns for synchronous operation that means max frequency should be 100Mhz only.

    The first forum post appears to be correct when stating that the maximum VCLK3 for both synchronous and asynchronous interfaces is 100 MHz, based on this timing specification.

    --
    Thanks & regards,
    Jagadish.