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AM2634: AM2634COLFHAZCZR with DP83869HM PHY bringup

Gogula PavanKumar
Prodigy 35 points

Part Number: AM2634
Other Parts Discussed in Thread: DP83869HM, SYSCONFIG

Hi Team

I am currently working on the AM2634COLFHAZCZR custom board with DP83869HM PHY bring-up, and I have installed the software packages from the link below. 
www.ti.com/.../08.05.00.24

After opening the Ethernet examples, I want to know which example is the simplest and most suitable for Ethernet bring-up.
My goal is only basic Ethernet bring-up.

I tested one of the examples, but it is not working on my custom board.

C:\ti\mcu_plus_sdk_am263x_08_05_00_24\examples\networking\lwip\enet_lwip_cpsw\am263x-cc\r5fss0-0_freertos

I need guidance on how to edit the example.syscfg file — specifically how to configure Ethernet and the PHY in the SysConfig file.

Please provide a step-by-step process, including any changes required in the example code and how to modify the project according to my custom board and PHY.

Could you please suggest this?

 

 

  • 0
    TI__Guru 61640 points

    Please use the latest version of SDK 11.01

    https://www.ti.com/tool/download/MCU-PLUS-SDK-AM263X/11.01.00.19

    It would be highly recomended to use this as the version you are using it more than 2 yrs old

  • 0
    TI__Guru 61640 points
    Gogula PavanKumar said:
    Please provide a step-by-step process, including any changes required in the example code and how to modify the project according to my custom board and PHY.

    Please refer to this  software-dl.ti.com/.../custom_enetphy_guide.html

  • 0 in reply to Nilabh Anand
    Prodigy 35 points

    Hi Nilabh Anand

    I have installed this version and chosen the example listed below.

    https://www.ti.com/tool/download/MCU-PLUS-SDK-AM263X/11.01.00.19

    C:\ti\mcu_plus_sdk_am263x_11_01_00_19\source\networking\enet\core\examples\lwip\enet_lwip_cpsw\am263x-cc\r5fss0-0_freertos.

    I edited the example.syscfg file based on my PHY (DP83869HM). After making these changes, I rebuilt the project and flashed it to the board.

    The UART log is showing only this output, and I am not getting an IP address. Flash successfully completed log. 

    Flash Sucessfully log

Cortex_R5_0: GEL Output: Loading Gel Files on R5F0 
Cortex_R5_0: GEL Output: Gel files loading on R5F0 Complete
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263x Initialization Scripts Launched. 
Please Wait...


Cortex_R5_0: GEL Output: AM263x_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present 
Cortex_R5_0: GEL Output: AM263x_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x00000000    
Cortex_R5_0: GEL Output: 
 QSPI - 4S Functional boot mode
Cortex_R5_0: GEL Output: AM263x_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA    
Cortex_R5_0: GEL Output: AM263x_Check_supported_mode() Launched
Cortex_R5_0: GEL Output: 
 The Device supports both LockStep & Dual Core mode 
Cortex_R5_0: GEL Output: 
 mode = 1 
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: 

*** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output: 

*** R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: 

 All R5F Cores Released for program load
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: PER PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output: 
 CLK Programmed R5F=400MHz and SYS_CLK=200MHz 
Cortex_R5_0: GEL Output: 

 *** Enabling Peripheral Clocks *** 
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks 
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks 
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks 
Cortex_R5_0: GEL Output: Enabling QSPI Clocks 
Cortex_R5_0: GEL Output: Enabling I2C Clocks 
Cortex_R5_0: GEL Output: Enabling TRACE Clocks 
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks 
Cortex_R5_0: GEL Output: Enabling GPMC Clocks 
Cortex_R5_0: GEL Output: Enabling ELM Clocks 
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks 
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks 
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks 
Cortex_R5_0: GEL Output: Enabling CPTS Clocks 
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks 
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks 
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks 
Cortex_R5_0: GEL Output: 

 ***All IP Clocks are Enabled*** 

Cortex_R5_0: AM2634
Cortex_R5_0: Board Selected : CC
Cortex_R5_0: GEL Output: CPU https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1620224/am2634-am2634colfhazczr-with-dp83869hm-phy-bringup/6248581#reset (soft reset) has been issued through GEL.

        

  • 0 in reply to Nilabh Anand
    Prodigy 35 points

    Hi Nilabh Anand

    I am checking the static IP process on Ethernet. I have enabled it.

    /* uncomment the next two lines for Static IP */
    #define USE_DHCP 0
    #define USE_AUTOIP 0

    The remaining code was not changed, but the Ethernet is still not detected.

    In test.c file

const ip_addr_t gStaticIP[IP_ADDR_POOL_COUNT]               =  { IPADDR4_INIT_BYTES(192, 168, 2, 200), /* For NetifIdx = 0 */
                                                                                                       IPADDR4_INIT_BYTES(  10,  64,  2, 200),}; /* For NetifIdx = 1 */

const ip_addr_t gStaticIPGateway[IP_ADDR_POOL_COUNT] =  { IPADDR4_INIT_BYTES(192, 168, 2, 100), /* For NetifIdx = 0 */
                                                                                                       IPADDR4_INIT_BYTES(  10,   64, 2, 100),}; /* For NetifIdx = 1 */

const ip_addr_t gStaticIPNetmask[IP_ADDR_POOL_COUNT] =  { IPADDR4_INIT_BYTES(255,255,255,0), /* For NetifIdx = 0 */
  • 0 in reply to Gogula PavanKumar
    TI__Guru 61640 points

    Have you set the local IP address of your machine to local IP address and gateway

  • 0 in reply to Nilabh Anand
    TI__Guru 61640 points

    Also can you attach the UART logs from the application, that will help me see the status of application

  • 0 in reply to Nilabh Anand
    Prodigy 35 points

    Hi Nilabh Anand

    I have configured the local IP address and gateway on my PC as follows:
    IP address: 192.168.1.100
    Gateway: 192.168.2.1

    UART logs are not coming, just one log only coming.

  • 0 in reply to Nilabh Anand
    Prodigy 35 points

    Hi Nilabh Anand
    I enabled debug logs in #include "lwipopts.h", but the debug logs are not appearing. I have attached my project files here. Please check and let me know if any modifications are required.

  • 0 in reply to Gogula PavanKumar
    TI__Guru 61640 points

    Hi,
    i am looking for UART logs from application, which should be like below:

    dev.ti.com/.../EXAMPLES_ENET_LWIP_CPSW_TCPCLIENT.html

    CPSW LWIP TCP CLIENT
    ==========================
    EnetPhy_bindDriver:1729
    PHY 3 is alive
    PHY 12 is alive
    Starting lwIP, local interface IP is dhcp-enabled
    Host MAC address-0 : 70:ff:76:1e:7e:52
    [LWIPIF_LWIP] NETIF INIT SUCCESS
    Enet IF UP Event. Local interface IP:0.0.0.0
    [LWIPIF_LWIP] Enet has been started successfully
    Waiting for network UP ...
    Waiting for network UP ...
    Cpsw_handleLinkUp:1323
    MAC Port 1: link up
    Network Link UP Event
    Waiting for network UP ...
    Enet IF UP Event. Local interface IP:192.168.1.10
    Network is UP ...
    TCP Client Menu:
    Enter TCP server IPv4 address:(example: 192.168.101.100)
    192.168.1.20
    IP eneterd is: 192.168.1.20
    <<<< ITERATION 1 >>>>
    Connecting to: 192.168.1.20:8888
    Connection with the server is established
    "Hello over TCP 1" was sent to the Server
    Successfully received the packet 1
    "Hello over TCP 2" was sent to the Server
    Successfully received the packet 2
    "Hello over TCP 3" was sent to the Server
    Successfully received the packet 3
    "Hello over TCP 4" was sent to the Server
    Successfully received the packet 4
    "Hello over TCP 5" was sent to the Server
    Successfully received the packet 5
    Connection closed
    <<<< ITERATION 2 >>>>
    Connecting to: 192.168.1.20:8888
    Connection with the server is established
    "Hello over TCP 1" was sent to the Server
    Successfully received the packet 1
    "Hello over TCP 2" was sent to the Server
    Successfully received the packet 2
    "Hello over TCP 3" was sent to the Server
    Successfully received the packet 3
    "Hello over TCP 4" was sent to the Server
    Successfully received the packet 4
    "Hello over TCP 5" was sent to the Server
    Successfully received the packet 5
    Connection closed
  • 0 in reply to Nilabh Anand
    Prodigy 35 points

    Hi Nibah Anand

    I am currently working on the Static IP method. I have shared the UART log. When I try to ping the IP address, it shows ‘Destination Unreachable.

    I given my PC address: 192.168.1.125

    Board IP address: 192.168.1.200

    In Static IP address

const ip_addr_t gStaticIP[IP_ADDR_POOL_COUNT] =
{
    IPADDR4_INIT_BYTES(192,168,1,200),   // Board IP
    IPADDR4_INIT_BYTES(10,64,1,200),
};

const ip_addr_t gStaticIPGateway[IP_ADDR_POOL_COUNT] =
{
    IPADDR4_INIT_BYTES(192,168,1,1),     // Router Gateway
    IPADDR4_INIT_BYTES(10,64,1,1),
};

const ip_addr_t gStaticIPNetmask[IP_ADDR_POOL_COUNT] =
{
    IPADDR4_INIT_BYTES(255,255,255,0),
    IPADDR4_INIT_BYTES(255,255,252,0),
};

  • 0 in reply to Gogula PavanKumar
    TI__Guru 61640 points

    I see link call back up missing in your logs,

    That means LwiP has not detected any link, that is the cause of the ping fails.

  • 0 in reply to Nilabh Anand
    Prodigy 35 points

    Hi Nilabh Anand

    I have shared my latest log, but the ping is not working. I need some information based on this. Please let me know what the issue might be and whether any changes are required in the software code or in the SysConfig file.

    Uart Log

=========================

      ENET LWIP App       

==========================

EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 

Mdio_open:318 

Open MAC port 1

PHY 3 is alive

[0]: Starting lwIP, local interface IP is 192.168.1.200

[LWIPIF_LWIP] NETIF INIT SUCCESS

Host MAC address-0 : 70:ff:76:1d:ec:f2


[LWIPIF_LWIP] Enet has been started successfully

[0]status_callback==UP, local interface IP is 192.168.1.200

UDP server listening on port 5001

Cpsw_handleExternalPhyLinkUp:1044 

[0] link_callback==UP

      7.733s : CPU load =   7.09 %

     12.733s : CPU load =   1.89 %

     17.733s : CPU load =   1.87 %

     22.733s : CPU load =   1.87 %

     27.733s : CPU load =   1.86 %

     32.733s : CPU load =   1.86 %

     37.733s : CPU load =   1.86 %

     42.733s : CPU load =   1.86 %

     47.733s : CPU load =   1.86 %

     52.733s : CPU load =   1.86 %

     57.733s : CPU load =   1.86 %

     62.733s : CPU load =   1.86 %

     67.733s : CPU load =   1.86 %

     72.733s : CPU load =   1.86 %

     77.733s : CPU load =   1.86 %

     82.733s : CPU load =   1.86 %

     87.733s : CPU load =   1.86 %

     92.733s : CPU load =   1.86 %

     97.733s : CPU load =   1.86 %

    Later, I changed the PING value to 1, but I am getting an log error as shown below.[lwipcfg.h file]

    #define LWIP_PING_APP 1

    // I changed PING value is 1, log is

==========================

      ENET LWIP App       

==========================

EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 

Mdio_open:318 

Open MAC port 1

PHY 3 is alive

[0]: Starting lwIP, local interface IP is 192.168.1.200

[LWIPIF_LWIP] NETIF INIT SUCCESS

Host MAC address-0 : 70:ff:76:1d:ec:f2


[LWIPIF_LWIP] Enet has been started successfully

[0]status_callback==UP, local interface IP is 192.168.1.200

UDP server listening on port 5001

UDP server: Error creating Socket

  • 0 in reply to Gogula PavanKumar
    Prodigy 35 points

    Please find the attached schematic for our custom board. Could you kindly review it, particularly at the Ethernet PHY level . Also, I would appreciate it if    could forward this request to the appropriate Ethernet PHY team on the forum for further verification.

    e2e.ti.com/.../6254991

    7558.CUSTOM_BOARD-REV02.pdf

    Thank you for your support.

  • 0 in reply to Gogula PavanKumar
    TI__Guru 61640 points

    Hi,

    It would be better to create a thread in the ethernet phy forum specifically, as I am not aware of which PHY expert to be looped in. I would really appreciate if you can do the same.

  • 0 in reply to Gogula PavanKumar
    TI__Guru 61640 points
    Gogula PavanKumar said:
    Later, I changed the PING value to 1, but I am getting an log error as shown below.[

    This is not needed, please revert it back, Ping  is enabled by default in the lwip stack.

    Can you try to run the examples to see if phy and mac loopback are working or not:

    software-dl.ti.com/.../EXAMPLES_ENET_CPSW_LOOPBACK.html

  • 0 in reply to Nilabh Anand
    Prodigy 35 points

    Hi Nilabh Anand

    Ping is not working and the loopback test is also failing. I have attached the log here. Please let me know what the possible issue might be and whether any changes are required in the software code or in the SysConfig file.


  • 0 in reply to Nilabh Anand
    Prodigy 35 points

    Hi Nilabh Anand,

    I hope you are doing well.

    I have documented all the SysConfig changes that were made to the example project in order to bring up Ethernet and attempt ping functionality on our custom board. I am attaching the detailed document along with the code zip file for your reference.

    Could you please review the document and the attached code from your end and also kindly verify it with your team/experts? We would greatly appreciate your guidance if any additional corrections or configurations are required.

    We are deeply expecting  your support would help us move forward and close this activity.


    Syscnfg file.docx
    enet_lwip_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang (1).zip

  • 0 in reply to Gogula PavanKumar
    TI__Mastermind 26702 points

    Hi,

    I reviewed your docx file. Can you please help me with the below data:

    1. PHY Loopback example:

    First run the PHY loopback example:

    1.1 make sure your hardware connections are fine,

    1.2 make sure you see PHY link up and PHY alive logs

    1.3 Please share the application logs that you see, compare with the logs here: software-dl.ti.com/.../EXAMPLES_ENET_CPSW_LOOPBACK.html

    1.4 Please share the CPSW_STATS after your application has executed (Even if failed).

    Steps to get CPSW_STATS: https://dev.ti.com/tirex/explore/node?node=A__AaBu6ik6ZY8v2032wjLx6Q__AM26X-ACADEMY__t0CaxbG__LATEST

    2. MAC Loopback example

    Next, run the MAC Loopback example:

    2.1 make sure your hardware connections are fine,

    2.2 make sure you see PHY link up and PHY alive logs, MAC Port open logs. compare with the logs here: software-dl.ti.com/.../EXAMPLES_ENET_CPSW_LOOPBACK.html

    2.3 Please share the application logs that you see

    2.4 Please share the CPSW_STATS after your application has executed (Even if failed).

    Steps to get CPSW stats: https://dev.ti.com/tirex/explore/node?node=A__AaBu6ik6ZY8v2032wjLx6Q__AM26X-ACADEMY__t0CaxbG__LATEST

    3. LWIP example:

    When running LWIP example, once you get the IP address, try to ping the device, once you see ping failure, halt the core and get the LWIP stats.

    Follow the steps here to get lwip stats: dev.ti.com/.../node

    Please share the above stats, which will help us understand the exact Ethernet behavior here

    Also, for the PHY part, requesting to create a separate thread in the PHY forum for quicker support.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 35 points

    Hi Shaunak Deshpande

    I have attached the debug log. It shows that there are no transmit or receive bits. Could you please help me check which configuration needs to be set in the SysConfig file?

  • 0 in reply to Gogula PavanKumar
    TI__Mastermind 26702 points

    Hi,

    The above means, no packets were recieved by the LwIP stack. Before we jump to sysconfig/ Software , we will have to make sure the Ethernet data-paths are working fine.

    Can you also share CPSW_STATS to see if the CPSW hardware received any packets?

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 35 points

    Hi Shaunak Deshpande

    I have documented all the SysConfig changes for your reference. Please review it and let me know if any changes are required.

    Debug log.docx

  • 0 in reply to Shaunak Deshpande
    Prodigy 35 points

    Hi Shaunak Deshpande

    EEPROM is required to store the MAC address. Since my custom board does not have an EEPROM, if I enable Auto MAC assignment in the SysConfig file, will an EEPROM be required?

  • 0 in reply to Gogula PavanKumar
    TI__Mastermind 26702 points

    Hi Pavan,

    We will have to modify the sysconfig template file as well, i will share the steps. The SDK examples are created for the default TI Eval kits which by default have the MAC address stored in the EEPROM. We will basically have to remove the dependency of sysconfig template files on the EEPROM APIs to read MAC address. Even if Auto-MAC assignment is enabled, at run-time it wont read from eeprom but to avoid build errors, we need to remove the EEPROM references.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 35 points

    Hi,

    Thank you for your reply. Could you please share the detailed steps? It would be very helpful to move forward in project.

  • 0 in reply to Gogula PavanKumar
    TI__Mastermind 26702 points

    Hi Pavan,

    I will provide this by end of the day today.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 35 points

    Hi Shaunak,
    Case 1: EEPROM Enabled (Default), MAC is Manual Entry

    • Custom Board:PING is not working.
    • EVL Board: PING is working.


    Case 2: CUSTOM_BOARD Option Enabled in SysConfig, MAC is Manual Entry

    • Custom Board: PING is not working.
    • EVL Board: Debug logs are not appearing.


    As per our understanding, since we are using the same components, the behavior should be the same for both the EVM board and our custom board.
    Kindly confirm if this behavior is expected and advise on the correct configuration to be used.

    Fullscreen Custom_Board.log Download 
      
==========================
      ENET LWIP App       
==========================
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 
Open MAC port 1
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
[0]: Starting lwIP, local interface IP is 192.168.1.200
[LWIPIF_LWIP] NETIF INIT SUCCESS
Host MAC address-0 : 70:ff:76:1d:ec:f2
[LWIPIF_LWIP] Enet has been started successfully
[0]status_callback==UP, local interface IP is 192.168.1.200
UDP server listening on port 5001
[0] link_callback==UP
      7.602s : CPU load =   3.64 %
     12.602s : CPU load =   0.74 %
     17.602s : CPU load =   0.74 %
     22.602s : CPU load =   0.74 %
     27.602s : CPU load =   0.74 %
     32.602s : CPU load =   0.74 %
     37.602s : CPU load =   0.74 %
     42.602s : CPU load =   0.74 %
     47.602s : CPU load =   0.74 %
     52.602s : CPU load =   0.74 %
     57.602s : CPU load =   0.74 %

    EVM.log

    Fullscreen Custom_Board_Checked.log Download 
                                                                                                                                                          
==========================
      ENET LWIP App       
==========================
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 
Open MAC port 1
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_WRITE_COMPLETE:471 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
Mdio_normal_ioctl_handler_ENET_MDIO_IOCTL_C22_ASYNC_READ_COMPLETE:396 
EnetMod_ioctl:1603 
[0]: Starting lwIP, local interface IP is 192.168.1.200
[LWIPIF_LWIP] NETIF INIT SUCCESS
Host MAC address-0 : 70:ff:76:1d:ec:f2
[LWIPIF_LWIP] Enet has been started successfully
[0]status_callback==UP, local interface IP is 192.168.1.200
UDP server listening on port 5001
[0] link_callback==UP
      8.594s : CPU load =   3.86 %
     13.594s : CPU load =   0.74 %
     18.594s : CPU load =   0.74 %
     23.594s : CPU load =   0.74 %
     28.594s : CPU load =   0.74 %
     33.594s : CPU load =   0.74 %
     38.594s : CPU load =   0.74 %
     43.594s : CPU load =   0.74 %
     48.594s : CPU load =   0.74 %
     53.594s : CPU load =   0.74 %
     58.594s : CPU load =   0.74 %
     63.594s : CPU load =   0.74 %
     68.594s : CPU load =   0.74 %
     73.594s : CPU load =   0.74 %
     78.594s : CPU load =   0.74 %
     83.594s : CPU load =   0.74 %
     88.594s : CPU load =   0.74 %
     93.594s : CPU load =   0.74 %
     98.594s : CPU load =   0.74 %
    103.594s : CPU load =   0.74 %
    108.594s : CPU load =   0.74 %

  • 0 in reply to Gogula PavanKumar
    TI__Mastermind 26702 points

    Hi,

    I've reached out to you over email. Lets get no a quick call, i would like to run some experiments on the custom board to verify the functionality.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 35 points

    Hi Shaunak,

    Thanks for reaching out. I’m available for a quick call—please let me know a convenient time. I’ll keep the custom board ready for testing.
    please share team meeting link 

    Thank you
    Pavan kumar

  • 0 in reply to Gogula PavanKumar
    Prodigy 35 points

    Hi Shaunak,

    As discussed in the meeting, could you please share the appropriate contact person’s email so that I can connect them with my TS team? They will proceed with the schematic review as per our discussion.

    Thank you
    Pavan kumar

  • 0 in reply to Shaunak Deshpande
    Prodigy 35 points

    Hi Shaunak

    We have tested with the latest version (11.0.1). The MAC loopback method is working fine, and we are currently checking the PHY loopback as well.

    I have shared the MAC loopback results—please have a look.

    Fullscreen MAC_Loop_log.log Download 
    =============================                                                                                                                                           
 Enet Loopback: Iteration 1                                                                                                                                             
=============================                                                                                                                                           
CPSW_3G Test                                                                                                                                                            
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:                                                                                        
0 From 4 To 2                                                                                                                                                           
Open MAC port 1                                                                                                                                                         
Setting in NO-PHY mode for MAC port 1                                                                                                                                   
initQs() txFreePktInfoQ initialized with 16 pkts                                                                                                                        
Received 5000 packets                                                                                                                                                   
Delete EnetApp_rxTask() and exit..                                                                                                                                      
Transmitted 5000 packets                                                                                                                                                
Delete EnetApp_txTask() and exit..                                                                                                                                      
                                                                                                                                                                        
 Port 0 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
                                                                                                                                                                        
 Port 1 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
Cpsw_handleLinkDown:1642                                                                                                                                                
Test complete: PASS                                                                                                                                                     
=============================                                                                                                                                           
 Enet Loopback: Iteration 2                                                                                                                                             
=============================                                                                                                                                           
CPSW_3G Test                                                                                                                                                            
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:                                                                                        
0 From 2 To 1                                                                                                                                                           
Open MAC port 1                                                                                                                                                         
Setting in NO-PHY mode for MAC port 1                                                                                                                                   
PHY 3 is alive                                                                                                                                                          
initQs() txFreePktInfoQ initialized with 16 pkts                                                                                                                        
Received 5000 packets                                                                                                                                                   
Delete EnetApp_rxTask() and exit..                                                                                                                                      
Transmitted 5000 packets                                                                                                                                                
Delete EnetApp_txTask() and exit..                                                                                                                                      
                                                                                                                                                                        
 Port 0 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
                                                                                                                                                                        
 Port 1 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
Cpsw_handleLinkDown:1642                                                                                                                                                
Test complete: PASS                                                                                                                                                     
=============================                                                                                                                                           
 Enet Loopback: Iteration 3                                                                                                                                             
=============================                                                                                                                                           
CPSW_3G Test                                                                                                                                                            
Open MAC port 1                                                                                                                                                         
Setting in NO-PHY mode for MAC port 1                                                                                                                                   
initQs() txFreePktInfoQ initialized with 16 pkts                                                                                                                        
Received 5000 packets                                                                                                                                                   
Delete EnetApp_rxTask() and exit..                                                                                                                                      
Transmitted 5000 packets                                                                                                                                                
Delete EnetApp_txTask() and exit..                                                                                                                                      
                                                                                                                                                                        
 Port 0 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
                                                                                                                                                                        
 Port 1 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
Cpsw_handleLinkDown:1642                                                                                                                                                
Test complete: PASS                                                                                                                                                     
=============================                                                                                                                                           
 Enet Loopback: Iteration 4                                                                                                                                             
=============================                                                                                                                                           
CPSW_3G Test                                                                                                                                                            
Open MAC port 1                                                                                                                                                         
Setting in NO-PHY mode for MAC port 1                                                                                                                                   
initQs() txFreePktInfoQ initialized with 16 pkts                                                                                                                        
Received 5000 packets                                                                                                                                                   
Delete EnetApp_rxTask() and exit..                                                                                                                                      
Transmitted 5000 packets                                                                                                                                                
Delete EnetApp_txTask() and exit..                                                                                                                                      
                                                                                                                                                                        
 Port 0 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
                                                                                                                                                                        
 Port 1 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
Cpsw_handleLinkDown:1642                                                                                                                                                
Test complete: PASS                                                                                                                                                     
=============================                                                                                                                                           
 Enet Loopback: Iteration 5                                                                                                                                             
=============================                                                                                                                                           
CPSW_3G Test                                                                                                                                                            
Open MAC port 1                                                                                                                                                         
Setting in NO-PHY mode for MAC port 1                                                                                                                                   
initQs() txFreePktInfoQ initialized with 16 pkts                                                                                                                        
Received 5000 packets                                                                                                                                                   
Delete EnetApp_rxTask() and exit..                                                                                                                                      
Transmitted 5000 packets                                                                                                                                                
Delete EnetApp_txTask() and exit..                                                                                                                                      
                                                                                                                                                                        
 Port 0 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
                                                                                                                                                                        
 Port 1 Statistics                                                                                                                                                      
-----------------------------------------                                                                                                                               
  rxGoodFrames            = 5000                                                                                                                                        
  rxBcastFrames           = 5000                                                                                                                                        
  rxOctets                = 2590000                                                                                                                                     
  txGoodFrames            = 5000                                                                                                                                        
  txBcastFrames           = 5000                                                                                                                                        
  txOctets                = 2590000                                                                                                                                     
  octetsFrames512to1023   = 10000                                                                                                                                       
  netOctets               = 5180000                                                                                                                                     
  txPri[0]                = 5000                                                                                                                                        
  txPriBcnt[0]            = 2590000                                                                                                                                     
                                                                                                                                                                        
Cpsw_handleLinkDown:1642                                                                                                                                                
Test complete: PASS                                                                                                                                                     
Loopback application completed                                                                                                                                          
All tests have passed!!

  • 0 in reply to Gogula PavanKumar
    TI__Mastermind 26702 points

    Hi Pavan Kumar,

    Gogula PavanKumar said:
    We have tested with the latest version (11.0.1). The MAC loopback method is working fine

    Can you please let me know what was changed which led to the software working?

    Can you also try an external loop-back (enet_layer2_cpsw example).

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 35 points

    Hi Shaubak Deshpande

    We have assigned the MAC address manually. While testing PHY loopback, we are only getting the below log. 

    External loop back(enet_layer2_cpsw example) also testing but error is coming. 

    Description	Resource	Path	Location	Type
fatal error: 'drivers/sciclient.h' file not found	l2_cpsw_common.h	/enet_l2_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang	line 47	C/C++ Problem
gmake: *** [l2_cpsw_cfg.o] Error 1	enet_l2_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang		 	C/C++ Problem
gmake: *** [l2_cpsw_dataflow.o] Error 1	enet_l2_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang		 	C/C++ Problem
gmake: *** [l2_cpsw_main.o] Error 1	enet_l2_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang		 	C/C++ Problem
gmake: Target 'all' not remade because of errors.	enet_l2_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang		 	C/C++ Problem
recipe for target 'l2_cpsw_cfg.o' failed	subdir_rules.mk	/enet_l2_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang/Release	line 52	C/C++ Problem
recipe for target 'l2_cpsw_dataflow.o' failed	subdir_rules.mk	/enet_l2_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang/Release	line 52	C/C++ Problem
recipe for target 'l2_cpsw_main.o' failed	subdir_rules.mk	/enet_l2_cpsw_am263x-cc_r5fss0-0_freertos_ti-arm-clang/Release	line 52	C/C++ Problem

  • 0 in reply to Gogula PavanKumar
    Prodigy 35 points

    Hi Shaunak,

    We have added an external EEPROM to our custom board.

    While testing the custom board, we observed that in MAC loopback, logs are printed properly when the MAC address is assigned manually. However, when auto MAC assignment is used, getting error in log

    Also, during PHY loopback testing, the logs are not coming properly even with EEPROM and with out EEPROM

    Please find the attached log for reference.

    Could you please help us  in this case?

    Fullscreen CUSTOM_AUTO_MAC_log.log Download 
    =============================
 Enet Loopback: Iteration 1
=============================
CPSW_3G Test
Assertion @ Line: 285 in syscfg/ti_board_config.c: ENET_GET_NUM_MAC_ADDR(numMacMax) <= ENET_BOARD_NUM_MACADDR_MAX : failed !!!


    Fullscreen CUSTOM_MAC_log.log Download 
    =============================
 Enet Loopback: Iteration 1
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2
Open MAC port 1
Setting in NO-PHY mode for MAC port 1
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1679
Test complete: PASS
=============================
 Enet Loopback: Iteration 2
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 1
Open MAC port 1
Setting in NO-PHY mode for MAC port 1
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1679
Test complete: PASS
=============================
 Enet Loopback: Iteration 3
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 1
Open MAC port 1
Setting in NO-PHY mode for MAC port 1
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1679
Test complete: PASS
=============================
 Enet Loopback: Iteration 4
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 1
Open MAC port 1
Setting in NO-PHY mode for MAC port 1
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1679
Test complete: PASS
=============================
 Enet Loopback: Iteration 5
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 1
Open MAC port 1
Setting in NO-PHY mode for MAC port 1
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1679
Test complete: PASS
Loopback application completed
All tests have passed!!


    Fullscreen CUSTOM_AUTO_PHY_Log.log Download 
    =============================
 Enet Loopback: Iteration 1
=============================
CPSW_3G Test


    Fullscreen CUSTOM_PHY_Log.log Download 
    =============================
 Enet Loopback: Iteration 1
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2
Open MAC port 1
EnetPhy_bindDriver:1873
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Cpsw_handleLinkUp:1653
Transmitted 5000 packets
Delete EnetApp_txTask() and exit..


    Thanks and Regards
    Pavan kumar