Part Number: AM2431
Other Parts Discussed in Thread: SYSCONFIG
We are using AM2431 with an LPDDR4 device (Winbond W66BP6NBUAFJ).
I have 2 questions regarding Errata i2160: "DDR: Valid VRef Range Must be Defined During LPDDR4 Command Bus Training".
According to the errata document, the LPDDR4 Command Bus Training (CBT) VRef search range should be limited to within ±4% of the nominal VRef value.
However, when I generate the DDR initialization header using SysConfig (version 0.10.32, AM64x DDR Register Configuration tool), the generated board_ddrReginit.h contains the following VRef search ranges:
- F0: 0–50
- F1: 30–50
- F2: 30–50
From my understanding, to comply with Errata i2160, these ranges should be restricted to approximately (VRef × 0.96) to (VRef × 1.04).
With the current SysConfig output, the CBT VRef range appears to exceed the ±4% recommendation.
My questions are:
1) Is it possible to configure SysConfig so that the generated Command Bus Training (CBT) VRef search range complies with Errata i2160?
In other words, can SysConfig itself be used to avoid Errata i2160, or is a manual modification of board_ddrReginit.h required?
In other words, can SysConfig itself be used to avoid Errata i2160, or is a manual modification of board_ddrReginit.h required?
2) The errata states: "Set the following fields to known valid working values before enabling CBT."
However, in the generated DDR initialization sequence, the following registers:
However, in the generated DDR initialization sequence, the following registers:
- EMIF_CTLCFG_DENALI_PI_199
- EMIF_CTLCFG_DENALI_PI_207
- EMIF_CTLCFG_DENALI_PI_208
appear to be written in an order that effectively occurs after CBT is enabled.
Strictly speaking, this seems to contradict the "before enabling CBT" requirement. Is this ordering safe by design, or is there a recommended workaround to ensure full compliance with Errata i2160?
appear to be written in an order that effectively occurs after CBT is enabled.
Strictly speaking, this seems to contradict the "before enabling CBT" requirement. Is this ordering safe by design, or is there a recommended workaround to ensure full compliance with Errata i2160?
Any guidance on the correct interpretation of the errata and the recommended SysConfig / DDR initialization flow would be greatly appreciated.CBT_RegisterVal.pdf W66BP6NB_W66CP2NQ_LPDDR4_datasheet_A01-004_20230324.pdf