Part Number: AM2431
Other Parts Discussed in Thread: DRA829J
I have a question regarding the PLL programming sequence on AM2431.
In the Technical Reference Manual (p.455–456), there is a table titled “Table 5-472. Programming Sequence of PLLCTRL, HSDIV, and PLL”.
In this table, several steps explicitly require a Delay (I count seven delay points), but the TRM does not specify the actual delay duration (for example, in microseconds or clock cycles).
My understanding is as follows, and please correct me if this is wrong:
- SYSFW internally performs a sequence equivalent to this table when configuring PLLs.
- For the steps marked as Delay, SYSFW likely inserts either:
- a fixed time delay (e.g. based on a timer), or
- a polling-based wait (e.g. waiting for PLL lock / status bits to change).
However, from the documentation, I cannot find:
- the actual delay values, or
- whether these delays are time-based or status-bit–based.
Could you please clarify:
-
How long is each Delay step?
- Are the delays implemented as fixed waits, or are they conditional waits (e.g. polling lock/status)?
Thank you for your support.
