MSPM0G3519: POR does not reset INITDONE

Hi Aaron,

A reset level higher than boot reset (includes both boot reset and POR reset) could both reset INITDONE.

Have you enabled CSCEXISTS and FLASHBANKSWAPPOLICY filed in NONMAIN for your CSC solution? These two filed should be enabled to enable CSC process, you could refer to point #5 of 3.2.4.3 CSC NONMAIN Configuration of Cybersecurity Enablers in MSPM0 MCUs (Rev. A) for more details.

Hello Pengfei,

CSCEXISTS and FLASHBANKSWAPPOLICY are both enabled. I am not having trouble entering CSC, I am never seeing INITDONE cleared by a POR. I see logs from the bootloader over uart, DL_SYSCTL_isINITDONEIssued() always returns true after a POR is issued, SECSTATUS always has a value of 0x1. When I am running in the main application and I call DL_SYSCTL_isExecuteFromUpperFlashBank() it always returns false, regardless of what image versions are in the two flash banks. I have included my CSC main application below. Is there some additional config that needs to be enabled to unlock the INITDONE flag? Is there some possible hardware issue that is stopping the MCU from completing a reset and clearing the INITDONE flag?

CSC main

int main(void)
{
uint8_t done = 0;
fih_int bootStatus;
struct boot_rsp bootRsp;
SYSCFG_DL_init();
MCUBOOT_LOG_INF("Starting bootloader\r\n");

/* Execution flow for the privileged state. Device has no features but
* static write protect enabled, and images are unverified, and
* therefore must be authenticated.
*/
MCUBOOT_LOG_INF("Checking initdone\r\n");
if (!DL_SYSCTL_isINITDONEIssued()) {
/* First boot - determine which bank to execute from and configure bank swap BEFORE INITDONE */
MCUBOOT_LOG_INF("First boot - determining bank selection\r\n");
boot_return_highest_version(&bootRsp);
bootStatus = boot_go(&bootRsp);

if ((0 == bootStatus) && (IMAGE_MAGIC == bootRsp.br_hdr->ih_magic)) {
MCUBOOT_LOG_INF("Image found: offset = 0x%x, ver=%d.%d.%d.%d\r\n",
bootRsp.br_image_off,
bootRsp.br_hdr->ih_ver.iv_major,
bootRsp.br_hdr->ih_ver.iv_minor,
bootRsp.br_hdr->ih_ver.iv_revision,
bootRsp.br_hdr->ih_ver.iv_build_num);

/* Configure bank swap BEFORE INITDONE */
if (bootRsp.br_image_off != PRIMARY_SLOT_OFFSET) {
MCUBOOT_LOG_INF("Configuring bank swap for upper flash bank\r\n");
DL_SYSCTL_executeFromUpperFlashBank();
} else {
MCUBOOT_LOG_INF("Configuring for lower flash bank (no swap)\r\n");
DL_SYSCTL_executeFromLowerFlashBank();
}
}

/* Set Firewalls (to be enabled upon INITDONE) */
DL_SYSCTL_setWriteProtectFirewallAddrRange(
(uint32_t) LOCKABLE_FLASH_FIREWALL);

MCUBOOT_LOG_INF("Issuing INITDONE\r\n");
DL_SYSCTL_issueINITDONE();
}

/* After INITDONE - boot from the configured bank */
MCUBOOT_LOG_INF("initdone is set\r\n");

MCUBOOT_LOG_INF("mcuboot_app\r\n");
boot_return_highest_version(&bootRsp);

bootStatus = boot_go(&bootRsp);
MCUBOOT_LOG_INF("boot_go returned %d\r\n", bootStatus);
if ((0 == bootStatus) && (IMAGE_MAGIC == bootRsp.br_hdr->ih_magic)) {
MCUBOOT_LOG_INF("bootRsp: slot = %x, offset = %x, ver=%d.%d.%d.%d\r\n",
bootStatus, bootRsp.br_image_off,
bootRsp.br_hdr->ih_ver.iv_major,
bootRsp.br_hdr->ih_ver.iv_minor,
bootRsp.br_hdr->ih_ver.iv_revision,
bootRsp.br_hdr->ih_ver.iv_build_num);

/* Determine which bank we're executing from */
uint32_t executing_bank;
if (bootRsp.br_image_off != PRIMARY_SLOT_OFFSET) {
MCUBOOT_LOG_INF("Executing from upper flash bank (after swap)\r\n");
executing_bank = 1;
} else {
MCUBOOT_LOG_INF("Executing from lower flash bank\r\n");
executing_bank = 0;
}

uint32_t current_version = bootRsp.br_hdr->ih_ver.iv_major << 24 |
(bootRsp.br_hdr->ih_ver.iv_minor << 16) |
(bootRsp.br_hdr->ih_ver.iv_revision << 8);
// Encode bank number in LSB of signature
uint32_t signature_with_bank = (SIGNATURE & 0xFFFFFFFE) | (executing_bank & 0x1);
MCUBOOT_LOG_INF("Writing version info to flash: version 0x%08x, signature 0x%08x (bank %d), address 0x%x\r\n",
current_version, signature_with_bank, executing_bank, FLASH_ADDR_FIRMWARE_VERSION);
// Write current execution bank to both banks for redundancy
write_version_info_to_flash(current_version, signature_with_bank, true);
write_version_info_to_flash(current_version, signature_with_bank, false);

} else {
MCUBOOT_LOG_ERR("Boot go failed\r\n");
mcubootFail();
}
do_boot(&bootRsp);
//should never get here
mcubootFail();
}

After some additional investigation I see that CSCEXISTS is always zero in SECSTATUS. I have CSCEXISTS enabled in syscfg and I see in the generated boot_config.c file that cscexists is getting set to 0xffff. However when I use the memory viewer to look at 41c00018 it is set to 0xaabb, which indicates that CSC does not exist. I also see in the steps for the CSC projects that .BCRConfig and .BSLConfig are removed when using objcopy to create the BIN. When I change the objcopy step to not remove BCRConfig and BSLConfig the output bin becomes 1Gb in size and cannot be used.

Objcopy step removing BSL and BCR
C:/ti/ccs2041/ccs/tools/compiler/ti-cgt-armllvm_4.0.4.LTS/bin/tiarmobjcopy customer_secure_code_metering_prod.out -R .BCRConfig -R .BSLConfig -R .TI.bound* --output-target binary customer_secure_code_metering_prod-bank1-0x40000.bin

My boot_config.c (not being used by build)