Hello all
The output stage of N2HET allows to combine two consecutive outputs to achieve a higher timer resolution or a symmetrical PWM. When working with pulses instead of set/clear for the two combined outputs, two inputs of the XOR/AND-gate change at the same time. (End of Program loop) Is the schematic (SPNU499 Figure 19-15) a simplification or do I have to expect a glitch at the output, caused by this race condition?
BR, Matthias