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Hello all
The output stage of N2HET allows to combine two consecutive outputs to achieve a higher timer resolution or a symmetrical PWM. When working with pulses instead of set/clear for the two combined outputs, two inputs of the XOR/AND-gate change at the same time. (End of Program loop) Is the schematic (SPNU499 Figure 19-15) a simplification or do I have to expect a glitch at the output, caused by this race condition?
BR, Matthias
Hello Matthias,
The XOR-shared and AND-shared outputs are intended to be used by applications that wish to output pulses smaller than the loop-resolution clock period. It is understood that the smallest intentional pulse that will be output will be one high-resolution clock period wide (XOR or two outputs offset by 1 HR period).
If the XOR-share or AND-share feature is used on output switching very close to each other (delay only due to relative timing differences), then there indeed is a possibility of outputting a glitch on the PWMs.
Regards,
Sunil
Hello Sunil
Thanks for the answer. I think we speak about something different. Of course, with the high resolution structure of N2HET it is possible to generate very short pulses. (That’s what I want, by the way.) But I’m not sure if I’m aware from glitches caused by the (more or less) simultaneous transition of the two inputs A and B at START of the loop. Assumed I generate signal A and B with PULSELO or PULSEHIGH, the signals are toggled back at start of each LR. Is there an additional latch after the gate that prevents this from leading in a race-condition?
Hello Matthias,
There is a de-glitching flop on the both the XOR-shared and the AND-shared outputs. We will update the N2HET documentation to show these flops. These flops are clocked by VCLK2.
Thank you for identifying this.
Regards,
Sunil