Part Number: AM263P4-Q1
Other Parts Discussed in Thread: SYSCONFIG
Hello Nilabh Anand
We are using Infineon S25FL128LAGMFB013 QSPI flash.
Further to your comment here: AM263P4-Q1: RBL / SBL Checklist? - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums
"A simple way to program is to run the OSPI flash io example to do read/write in 4s mode, in the program, configure the QE bit."
Question 1:
The .json file produced by the diagnostic example (attached) for the Infineon device has the following:
"p114": {
"isDtr": false,
"cmdRd": "0x6C",
"cmdWr": "0x34",
"modeClksCmd": 0,
"modeClksRd": 0,
"dummyClksCmd": 0,
"dummyClksRd": 8,
"enableType": "5",
"enableSeq": "0x00",
"dummyCfg": null,
"protoCfg": null,
"strDtrCfg": null
},
Where it says "enableType": "5" is this the QE enable type for protocol 1S-1S-4S?
Question 2:
If so, after clicking the 'LOAD FROM JSON" button then selecting 1S-1S-4S, the Quad Enable Type remains at '0'. Why isn't the Enable Type set to '5'?
Question 3:
The SysCfg help for Quad Enable Type 5 says:
"5 : QE is bit 1 of the status register 2"
However, the datasheet for my Infineon device does not mention anything about QE bit in either of Status Register 1 or 2. It does however, mention QE bit is bit 1 of "Configuration Register 1":
Could you confirm the text is correct in the SysCfg help please?


