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Original question:

AM2434: Understanding AM2434 performance

AM2434: AM2434 performance questions

Gael Le Moing
Prodigy 130 points

Part Number: AM2434

Hi,

Question related to the original thread: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1617634/am2434-understanding-am2434-performance/6321976

About the measurements performed buy TI team (see picture)

TI_Support_benchmark App 2500KB AM2434.png

  • In the different columns, in which memory was the main stack located?
  • What compiler optimization level was set (-O1, -O2, -O3, -Og, …)?
  • On my side, DDR execution compared to MSRAM (first and third column from the TI table above) was around 2.8 longer, but 1.8x longer on TI side. There could be differences on the application design, but are there any specific settings applied somewhere around the DDR controller in your benchmarks? On my side, I used DDR config from SDK, but I also regenerated a DDR config using the DDR config online tool and I had the same results.

 

Best regards,

Gael

 

  • 0
    TI__Guru* 93551 points

    Hi Gael, for your 3rd question, what changes did you make to your DDR config?  Was same frequency configured?  I'm pretty sure the default config (from the tool) was used for these benchmarks.

    James

  • 0 in reply to JJD
    Prodigy 130 points

    Hi,

    I did not make any changes: I just took the default DDR config coming from AM2434 EVM config in the tool. I was wondering if the online tool may have incorporated any update compared to the SDK version I was using (motor_control_sdk_am243x_11_00_00_06).

    The frequency is 400MHz for 1600MT/s. Here is an extract of the generated file (last week, if I recall):

  • 0 in reply to Gael Le Moing
    TI__Guru* 93551 points

    There may be some differences in the DDR config, but i don't think that would contribute to the differences in performance you are seeing.  This seems more likely to be a software differences which are causing different measurements.  I will loop the sw team in.

    Regards,

    james

  • 0 in reply to JJD
    Prodigy 130 points

    Ok, thanks, especially for the two first questions (stack location and compiler optimization level. If we used the same for both, then I agree with you that it should be due to the software itself.

    Regards,

    Gael

  • 0 in reply to Gael Le Moing
    TI__Intellectual 1620 points

    Hi Gael,

    The difference between the numbers (2.8x vs 1.8x) would arise from the different sizes of the code and data that the CPU executes directly from DDR. The above table was obtained by benchmarking the OCMC Benchmarking example. Similar numbers to the table would be obtained if this example is being used.

    Upon, reviewing the screenshot shared by   in the previous thread, , the screenshot is incomplete.

    Please find correct screenshot below:

    Regards,

    Aryamaan