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Original question:

AM263P4: ADC

AM263P4-Q1: Query regarding the ADC_REFBUF0_CTRL register is used to enable ADC Reference Buffer 0.

Shilpa G
Prodigy 140 points

Part Number: AM263P4-Q1

Hi Team,

I am working on the ADC peripheral on the AM263P4-CC board. For ADC conversion, I am following the sequence below:

  1. Enable ADC clock

  2. Enable ADC reference

  3. Configure ADC input range

  4. Power up the ADC core

  5. Initialize ADC configuration

  6. Configure ADC interrupt

  7. Periodically scan a fixed ADC channel

However, I am facing an issue while enabling the ADC reference buffer for the ADC0 instance when implementing the clock configuration from scratch in bare-metal code.

As per the TRM, I have followed the recommended sequence for configuring the Core PLL, Peripheral PLL, SYSCLK, and R5SS PLL clocks. Despite this, I am unable to enable ADC Reference Buffer 0 by setting the ADC_REFBUF0_CTRL register for the ADC0 instance.

Could you please help identify if there are any additional clock, power, reset, or unlock dependencies required before accessing this register?

Thanks,
Shilpa

 
  • 0
    TI__Expert 8390 points

    Hi Shilpa,

    For this issue, I would first check the Control MMR access sequence. The ADC reference enable is not only an ADC wrapper configuration. The ADC reference control is done through the CONTROLSS Control MMR path, so if the clock/startup code is being implemented from scratch, make sure the CONTROLSS Control MMR partition is unlocked before writing the ADC reference buffer/control registers. The SDK uses the Control MMR unlock mechanism, for example with SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, CONTROLSS_CTRL_PARTITION0). Also, confirm that the write is going to the CONTROLSS/Control MMR address for the ADC reference control, not to an offset from ADC0_BASE. The ADC reference buffer registers are part of the SOC/control configuration path, not the normal ADC0 wrapper register space.

    As a debug step, I recommend comparing the bare-metal sequence against the SDK-generated initialization, or temporarily calling the SDK SOC-level APIs such as SOC_enableAdcReference(0) / SOC_enableAdcInternalReference(0, TRUE) to isolate whether the issue is due to MMR unlock/addressing versus ADC0 clock/reset configuration.
    So the main dependencies to check are: ADC0 clock ungate, CONTROLSS Control MMR unlock, correct reference-control register address, ADC reset/power-up sequence, and the physical reference source configuration on the board.

    Best Regards,

    Masoud