Part Number: RM57L843
Hello,
I am looking for a solution to put the TI RM57L843 into sleep mode. To verify whether the clock domains and sources are successfully turned off, I am monitoring the ECLK pin on the MCU.
Note that application is executed from flash but sleep procedure is executed from RAM(in order to allow turn off flash).
I am using the following procedure to put the CPU into sleep mode:
1. Disable all non-CPU bus masters.
2. Put all I/Os into sleep mode.
3. Disable the unnecessary clock domains using the CDDIS register (VCLK, VCLK2, VCLKA1, RTI, VCLK3, VCLK4).
4. Set the clock sources for wakeup (to HF LPO), during sleep mode (to LF LPO), and the current clock source (to HF LPO) using the GHVSRC register.
5. Disable LPO CLKDET.
6. Disable the unnecessary clock sources using the CSDIS register (EXTCLK2, PLL2, HFLPO, LFLPO, EXTCLK).
7. Program the flash banks and flash pump fallback modes to "sleep"
8. Disable all remaining clock sources using CSDIS (OSC, PLL1).
9. Disable the remaining clock domains using CDDIS (HCLK, GCLK).
10. Idle the Cortex-R5F core using the WFI instruction.
The Issue:
After executing the procedure above, all clock domains are successfully turned off. However, there is an issue with disabling the clock sources: OSC and HF LPO remain active.
Since the CSDIS register is set to disable these clock sources, all clock domains are OFF, and the WFI command has been reached, what else could be causing this behavior?
Thank you for your help.
