• State
  • Replies 2 replies
  • Subscribers 32 subscribers
  • Views 21 views
  • Users 0 members are here
Support feedback
Options
Options
Related

Original question:

UNIFLASH: Erase content before programming

AM263P4: Uniflash CLI Erase command

Richard Xavier George
Prodigy 10 points

Part Number: AM263P4
Other Parts Discussed in Thread: UNIFLASH

I am using uniflash CLI to program the application.  I wanted to perform erase before programming to ensure there is no old data residing in the non programmed regions.

I tried the below command to erase but it did not work . From the log, I could see it returning invalid operation.

-c user_files/configs/AM263Px_ZCZ_F.ccxml -l user_files/settings/generated.ufsettings -e -b Erase

Then I tried to modify command to EraseAll as below and could see it working.

-c user_files/configs/AM263Px_ZCZ_F.ccxml -l user_files/settings/generated.ufsettings -e -b EraseAll

Could you confirm is this right command for erase operation ? I do not see relevant information about this in user guide.

Regards,
Richard

 

  • 0
    TI__Expert 7035 points

    Hi Richard,

    Thanks for the query. I am checking this from my side. I will get back to you asap.

    Thanks & Regards,

    Aswin

  • 0 in reply to Aswin Sankar
    TI__Expert 7035 points

    Hi Richard, 

    Can you please follow the below steps to enable erase using the Uniflash CLI tool

    1. Erase all: ./dslite-Cortex_R5_0.bat --config=user_files/configs/AM263Px_ZCZ_F.ccxml -b EraseAll

    2. Erase certain block: .\dslite-Cortex_R5_0.bat --config=user_files/configs/AM263Px_ZCZ_F.ccxml -s StandaloneEraseSpecificText=5 -b EraseBlocks

    3. Erase a range of blocks: .\dslite-Cortex_R5_0.bat --config=user_files/configs/AM263Px_ZCZ_F.ccxml -s StandaloneEraseSpecificText=0-10 -b EraseBlocks

    4. Erase a mixed range of blocks: .\dslite-Cortex_R5_0.bat --config=user_files/configs/AM263Px_ZCZ_F.ccxml -s "StandaloneEraseSpecificText=0-5,8" -b EraseBlocks

    The below log is expected in case of Erase All

    Cortex_R5_0: GEL Output: Gel files loading Complete
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. 
Please Wait...


Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present 
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B    
Cortex_R5_0: GEL Output: Dev Boot Mode 
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA    
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001    
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000    
Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode 
Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode 
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001    
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000    
Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode 
Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode 
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz 
Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
Cortex_R5_0: GEL Output: 

 *** Enabling Peripheral Clocks *** 
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks 
Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks 
Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks 
Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: Enabling OSPI Clocks 
Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
Cortex_R5_0: GEL Output: Enabling I2C Clocks 
Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling TRACE Clocks 
Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks 
Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks 
Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks 
Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks 
Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
Cortex_R5_0: GEL Output: Enabling CPTS Clocks 
Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks 
Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks 
Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks 
Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
Cortex_R5_0: GEL Output: 

 ***All IP Clocks are Enabled*** 

info: Cortex_R5_0: AM263Px_ZCZ_F
info: Cortex_R5_0: Board Selected : EVM
info: Cortex_R5_0: Part Selected : SIP (On-Chip Flash)
info: Cortex_R5_0: Erasing 1 Block ..
info: Cortex_R5_0: Erasing 2 Block ..
info: Cortex_R5_0: Erasing 3 Block ..
info: Cortex_R5_0: Erasing 4 Block ..
info: Cortex_R5_0: Erasing 5 Block ..
info: Cortex_R5_0: Erasing 6 Block ..
info: Cortex_R5_0: Erasing 7 Block ..
info: Cortex_R5_0: Erasing 8 Block ..
info: Cortex_R5_0: Erasing 9 Block ..
info: Cortex_R5_0: Erasing 10 Block ..
info: Cortex_R5_0: Erasing 11 Block ..
info: Cortex_R5_0: Erasing 12 Block ..
info: Cortex_R5_0: Erasing 13 Block ..
info: Cortex_R5_0: Erasing 14 Block ..
info: Cortex_R5_0: Erasing 15 Block ..
info: Cortex_R5_0: Erasing 16 Block ..
info: Cortex_R5_0: Erasing 17 Block ..
info: Cortex_R5_0: Erasing 18 Block ..
info: Cortex_R5_0: Erasing 19 Block ..
info: Cortex_R5_0: Erasing 20 Block ..
info: Cortex_R5_0: Erasing 21 Block ..
info: Cortex_R5_0: Erasing 22 Block ..
info: Cortex_R5_0: Erasing 23 Block ..
info: Cortex_R5_0: Erasing 24 Block ..
info: Cortex_R5_0: Erasing 25 Block ..
info: Cortex_R5_0: Erasing 26 Block ..
info: Cortex_R5_0: Erasing 27 Block ..
info: Cortex_R5_0: Erasing 28 Block ..
info: Cortex_R5_0: Erasing 29 Block ..
info: Cortex_R5_0: Erasing 30 Block ..
info: Cortex_R5_0: Erasing 31 Block ..
info: Cortex_R5_0: Erasing 32 Block ..
info: Cortex_R5_0: Erasing 33 Block ..
info: Cortex_R5_0: Erasing 34 Block ..
info: Cortex_R5_0: Erasing 35 Block ..
info: Cortex_R5_0: Erasing 36 Block ..
info: Cortex_R5_0: Erasing 37 Block ..
info: Cortex_R5_0: Erasing 38 Block ..
info: Cortex_R5_0: Erasing 39 Block ..
info: Cortex_R5_0: Erasing 40 Block ..
info: Cortex_R5_0: Erasing 41 Block ..
info: Cortex_R5_0: Erasing 42 Block ..
info: Cortex_R5_0: Erasing 43 Block ..
info: Cortex_R5_0: Erasing 44 Block ..
info: Cortex_R5_0: Erasing 45 Block ..
info: Cortex_R5_0: Erasing 46 Block ..
info: Cortex_R5_0: Erasing 47 Block ..
info: Cortex_R5_0: Erasing 48 Block ..
info: Cortex_R5_0: Erasing 49 Block ..
info: Cortex_R5_0: Erasing 50 Block ..
info: Cortex_R5_0: Erasing 51 Block ..
info: Cortex_R5_0: Erasing 52 Block ..
info: Cortex_R5_0: Erasing 53 Block ..
info: Cortex_R5_0: Erasing 54 Block ..
info: Cortex_R5_0: Erasing 55 Block ..
info: Cortex_R5_0: Erasing 56 Block ..
info: Cortex_R5_0: Erasing 57 Block ..
info: Cortex_R5_0: Erasing 58 Block ..
info: Cortex_R5_0: Erasing 59 Block ..
info: Cortex_R5_0: Erasing 60 Block ..
info: Cortex_R5_0: Erasing 61 Block ..
info: Cortex_R5_0: Erasing 62 Block ..
info: Cortex_R5_0: Erasing 63 Block ..
info: Cortex_R5_0: Erasing 64 Block ..

    Thanks & Regards,

    Aswin