AM263P4: OSPI interfacing at the same time flash and sram

michele sponchiado said:

it seems that AM263P4 cannot easily interface at the same time both a PSRAM and a Flash chip using OSPI interface and OSPI_CS{0,1} without tweaking some OSPI register to set/reset the chip selects.

We have not tested PSRAM interfacing on AM263Px, AM261x has been tested with PSRAM interface https://software-dl.ti.com/mcu-plus-sdk/esd/AM261X/latest/exports/docs/api_guide_am261x/EXAMPLES_DRIVERS_OSPI_PSRAM_IO.html

You can look at AM2612 device, which has two OSPI Interface - one for flash and one for PSRAM

https://www.ti.com/product/AM2612

michele sponchiado said:

I mean: it seems not feasible on AM263P4 to access the Flash on a specified address range using CS0 and the PSRAM on a different address range using CS1: is this correct?

Again this is not validated on TI side.

Hi, Nilabh!

Many thanks for your reply!

In the question https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1589266/am263p4-using-multiple-devices-via-ospi-select-chips?tisearch=e2e-sitesearch&keymatch=AM263P4%252520PSRAM Is stated that:

You are correct in your understanding. The AM263P4 has a single OSPI controller, and unlike the EMIF on the TMS570LC4357 where different address ranges automatically handle chip selects for different devices, the OSPI implementation works differently:

AM263P4 OSPI Limitations:

• The OSPI memory-mapped regions share the same address space

• Chip select switching is controlled via register configuration, not by address decoding

• You cannot access both PSRAM and Flash simultaneously through memory-mapped regions

• To switch between devices, you need to reconfigure the chip select in the OSPI controller registers

• ...

I see in the reg addendum pdf you suggested that it seems that it would instead be possible to select the active target upon the actual AHB address, i.e. the memory region address of the OSPI can be partitioned:

•  OSPI_FLASH_CFG_CONFIG_REG, bit 23 , ENABLE_AHB_DECODR_FLD. RW
  • Enable AHB Decoder: Value
    0 : Active target is selected based on Peripheral Chip Select Lines
    [bits [13:10]]. Value=1 Active target is selected based on actual AHB
    address [the partition for each device is calculated with respect to
    bits [28:21] of Device Size Configuration Register]
•  OSPI_FLASH_CFG_DEV_SIZE_CONFIG_REG
  • MEM_SIZE_ON_CS{3, 2, 1, 0}_FLD bit {28:27, 26:25, 24:23, 22:21}
  • Size of Flash Device connected to CS[{3, 2, 1, 0}] pin
    • 00 : size of 512Mb.
    • 01 : size of 1Gb.
    • 10 : size of 2Gb.
    • 11 : size of 4Gb.

I wonder if this means that setting e.g.:

• MEM_SIZE_ON_CS3 = 00b
• MEM_SIZE_ON_CS2 = 00b
• MEM_SIZE_ON_CS1 = 00b
• MEM_SIZE_ON_CS0 = 00b
• ENABLE_AHB_DECODR_FLD = 1
• (and probably a lot of other settings)
• then:
  • CS0 would be automagically active for addresses in the first 512Mbytes of the OSPI address space
    • I suppose just 128MBytes can be addressed, 0x6000 0000 up to 67ff ffff
    • CS{3, 2, 1} not active
  • CS1 would be automagically active for addresses in the second 512Mbytes of the OSPI address space
    • again, I suppose just 128MBytes can be addressed, 0x8000 0000 up to 87ff ffff
    • CS{3, 2, 0} not active

Many thanks again

Many thanks for your fast reply, Nilabh!

Now I need to bang my head a little digging into the example you are referring to, then I'll let you know if I have further questions!

Michele

Hi, Nilabh!

I wonder if carefully choosing the flash and psram chips so that the commands set would be compatible, then we would overcome the fact that the OSPI controller is unique and we could access both chips at the same time with automatic CS switching address-based without headaches