UNIFLASH: Although the UniFlash standalone command-line log reports a write failure, the program starts successfully.

ATSUKI IMADA

Part Number: UNIFLASH
Other Parts Discussed in Thread: LP-AM263P

We are currently developing a new product and plan to use the UniFlash Standalone Command Line tool to program software during the mass production process.

We are using UniFlash version 9.0.0. After configuring the software image to be programmed, we generate batch files using the Standalone Command Line feature and perform programming through the CLI.

In our current setup, the SBL and APPIMAGE are programmed using separate batch files. These batch files are then executed sequentially through another wrapper batch file.

After the programming of the SBL and APPIMAGE is completed, the following errors are reported. However, the software appears to be successfully written to the device, and the product boots correctly.

For the SBL, the first attempt fails while the second attempt succeeds. For the APPIMAGE, the first programming attempt stops partway through and results in a timeout error.

Could you please clarify:

What is causing these errors?
What are the recommended countermeasures or solutions?
Can these errors be safely ignored if the software is successfully programmed and the device boots normally?

The error logs are shown below.

SBL

error: Cortex_R5_0: Error Code 40000001

error: Cortex_R5_0: Error Loading the data...

error: Cortex_R5_0: Run failed...

error: Cortex_R5_0: File Loader: Failed to terminate flash programming: Algorithm indicated it failed to flash the data

Failed: File: SBL/user_files/images/loader.tiimage: Load failed.

APPIMAGE

Log when the process stops midway (1st attempt)

error: Cortex_R5_0: Run failed...

error: Cortex_R5_0: Trouble Removing Breakpoint with the Action "Remain Halted" at 0x7000c3a8: (Error -1066 @ 0x7000C3A8) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 20.0.0.3298)

error: Cortex_R5_0: File Loader: Failed to terminate flash programming: Timed out waiting for target to halt while executing flasher_jtag_uniflash_am263px-lp_r5fss0-0_nortos_ti-arm-clang.out

Failed: File: HWCAPP/user_files/images/myprogram.appimage: Load failed.

Log when the application boots successfully

error: Cortex_R5_0: Error Code 40000001

error: Cortex_R5_0: Error Loading the data...

error: Cortex_R5_0: Run failed...

error: Cortex_R5_0: File Loader: Failed to terminate flash programming: Algorithm indicated it failed to flash the data

Failed: File: HWCAPP/user_files/images/myprogram.appimage: Load failed.

For reference, the complete logs are attached below.

C:\Users\*\Downloads\test_bat\test_bat>call ./SBL/dslite-Cortex_R5_0.bat
Executing default command:
> dslite --mode flash -c SBL/user_files/configs/AM263Px_ZCZ_C.ccxml -l SBL/user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -e -f -v "SBL/user_files/images/loader.tiimage,0x60000000"

DSLite version 20.0.0.3619
Configuring Debugger (may take a few minutes on first launch)...
Initializing Register Database...
Initializing: DEBUGSSM_0
Executing Startup Scripts: DEBUGSSM_0
Initializing: CS_DAP_0
Executing Startup Scripts: CS_DAP_0
Initializing: Cortex_R5_0
Executing Startup Scripts: Cortex_R5_0
Cortex_R5_0: GEL Output: Gel files loading on R5F0 Complete
Initializing: Cortex_R5_1
Executing Startup Scripts: Cortex_R5_1
Initializing: Cortex_R5_2
Executing Startup Scripts: Cortex_R5_2
Initializing: Cortex_R5_3
Executing Startup Scripts: Cortex_R5_3
Initializing: Cortex_M4_0
Executing Startup Scripts: Cortex_M4_0
Initializing: ICSSM_PRU_0
Executing Startup Scripts: ICSSM_PRU_0
Initializing: ICSSM_PRU_1
Executing Startup Scripts: ICSSM_PRU_1
Initializing: CSSTM_0
Executing Startup Scripts: CSSTM_0
Initializing: CS_ETB_0
Executing Startup Scripts: CS_ETB_0
Connecting...
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.
Please Wait...

Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
Cortex_R5_0: GEL Output:
OSPI - 8S Functional Boot Mode
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000100
Cortex_R5_0: GEL Output: r5fss1 = 0x00000100
Cortex_R5_0: GEL Output:
R5FSS0 is in Lockstep mode
Cortex_R5_0: GEL Output:
R5FSS1 is in Lockstep mode
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:

*** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output:

***R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: PER PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:

*** Enabling Peripheral Clocks ***
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
Cortex_R5_0: GEL Output: Enabling QSPI Clocks
Cortex_R5_0: GEL Output: Enabling I2C Clocks
Cortex_R5_0: GEL Output: Enabling TRACE Clocks
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
Cortex_R5_0: GEL Output: Enabling CPTS Clocks
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

info: Cortex_R5_0: AM263Px_ZCZ_C
info: Cortex_R5_0: Board Selected : LP
info: Cortex_R5_0: Part Selected : Standard
Loading Program: SBL/user_files/images/loader.tiimage
Preparing ...
0 of 32752 at 0x60000000
0 of 32752 at 0x60007ff0: 14%
0 of 32752 at 0x6000ffe0: 29%
0 of 32752 at 0x60017fd0: 43%
0 of 32752 at 0x6001ffc0: 58%
0 of 32752 at 0x60027fb0: 72%
0 of 28236 at 0x6002ffa0: 87%
Finished: 87%
info: Cortex_R5_0: Writing 1 chunk at offset 0x0
info: Cortex_R5_0: Writing 2 chunk at offset 0x10000
info: Cortex_R5_0: Writing 3 chunk at offset 0x20000
info: Cortex_R5_0: Writing 4 chunk at offset 0x30000
error: Cortex_R5_0: Error Code 40000001
error: Cortex_R5_0: Error Loading the data...
error: Cortex_R5_0: Run failed...
error: Cortex_R5_0: File Loader: Failed to terminate flash programming: Algorithm indicated it failed to flash the data
Failed: File: SBL/user_files/images/loader.tiimage: Load failed.
Executing default command:
> dslite --mode flash -c HWCAPP/user_files/configs/AM263Px_ZCZ_C.ccxml -l HWCAPP/user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -e -f -v "HWCAPP/user_files/images/myprogram.appimage,0x60081000"

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.
Please Wait...

Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
Cortex_R5_0: GEL Output:
OSPI - 8S Functional Boot Mode
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
Cortex_R5_0: GEL Output:
R5FSS0 is in Dual-Core mode
Cortex_R5_0: GEL Output:
R5FSS1 is in Dual-Core mode
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:

*** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output:

***R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

info: Cortex_R5_0: AM263Px_ZCZ_C
info: Cortex_R5_0: Board Selected : LP
info: Cortex_R5_0: Part Selected : Standard
Loading Program: HWCAPP/user_files/images/myprogram.appimage
Preparing ...
0 of 32752 at 0x60081000
0 of 32752 at 0x60088ff0
0 of 32752 at 0x60090fe0: 1%
0 of 32752 at 0x60098fd0: 2%
0 of 32752 at 0x600a0fc0: 3%
0 of 32752 at 0x600a8fb0: 4%
0 of 32752 at 0x600b0fa0: 4%
0 of 32752 at 0x600b8f90: 5%
0 of 32752 at 0x600c0f80: 6%
0 of 32752 at 0x600c8f70: 7%
0 of 32752 at 0x600d0f60: 8%
0 of 32752 at 0x600d8f50: 8%
0 of 32752 at 0x600e0f40: 9%
0 of 32752 at 0x600e8f30: 10%
0 of 32752 at 0x600f0f20: 11%
0 of 32752 at 0x600f8f10: 12%
0 of 32752 at 0x60100f00: 12%
0 of 32752 at 0x60108ef0: 13%
0 of 32752 at 0x60110ee0: 14%
0 of 32752 at 0x60118ed0: 15%
0 of 32752 at 0x60120ec0: 16%
0 of 32752 at 0x60128eb0: 16%
0 of 32752 at 0x60130ea0: 17%
0 of 32752 at 0x60138e90: 18%
0 of 32752 at 0x60140e80: 19%
0 of 32752 at 0x60148e70: 20%
0 of 32752 at 0x60150e60: 20%
0 of 32752 at 0x60158e50: 21%
0 of 32752 at 0x60160e40: 22%
0 of 32752 at 0x60168e30: 23%
0 of 32752 at 0x60170e20: 24%
0 of 32752 at 0x60178e10: 24%
0 of 32752 at 0x60180e00: 25%
0 of 32752 at 0x60188df0: 26%
0 of 32752 at 0x60190de0: 27%
0 of 32752 at 0x60198dd0: 28%
0 of 32752 at 0x601a0dc0: 28%
0 of 32752 at 0x601a8db0: 29%
0 of 32752 at 0x601b0da0: 30%
0 of 32752 at 0x601b8d90: 31%
0 of 32752 at 0x601c0d80: 32%
0 of 32752 at 0x601c8d70: 32%
0 of 32752 at 0x601d0d60: 33%
0 of 32752 at 0x601d8d50: 34%
0 of 32752 at 0x601e0d40: 35%
0 of 32752 at 0x601e8d30: 36%
0 of 32752 at 0x601f0d20: 36%
0 of 32752 at 0x601f8d10: 37%
0 of 32752 at 0x60200d00: 38%
0 of 32752 at 0x60208cf0: 39%
0 of 32752 at 0x60210ce0: 40%
0 of 32752 at 0x60218cd0: 40%
0 of 32752 at 0x60220cc0: 41%
0 of 32752 at 0x60228cb0: 42%
0 of 32752 at 0x60230ca0: 43%
0 of 32752 at 0x60238c90: 44%
0 of 32752 at 0x60240c80: 45%
0 of 32752 at 0x60248c70: 45%
0 of 32752 at 0x60250c60: 46%
0 of 32752 at 0x60258c50: 47%
0 of 32752 at 0x60260c40: 48%
0 of 32752 at 0x60268c30: 49%
0 of 32752 at 0x60270c20: 49%
0 of 32752 at 0x60278c10: 50%
0 of 32752 at 0x60280c00: 51%
0 of 32752 at 0x60288bf0: 52%
0 of 32752 at 0x60290be0: 53%
0 of 32752 at 0x60298bd0: 53%
0 of 32752 at 0x602a0bc0: 54%
0 of 32752 at 0x602a8bb0: 55%
0 of 32752 at 0x602b0ba0: 56%
0 of 32752 at 0x602b8b90: 57%
0 of 32752 at 0x602c0b80: 57%
0 of 32752 at 0x602c8b70: 58%
0 of 32752 at 0x602d0b60: 59%
0 of 32752 at 0x602d8b50: 60%
0 of 32752 at 0x602e0b40: 61%
0 of 32752 at 0x602e8b30: 61%
0 of 32752 at 0x602f0b20: 62%
0 of 32752 at 0x602f8b10: 63%
0 of 32752 at 0x60300b00: 64%
0 of 32752 at 0x60308af0: 65%
0 of 32752 at 0x60310ae0: 65%
0 of 32752 at 0x60318ad0: 66%
0 of 32752 at 0x60320ac0: 67%
0 of 32752 at 0x60328ab0: 68%
0 of 32752 at 0x60330aa0: 69%
0 of 32752 at 0x60338a90: 69%
0 of 32752 at 0x60340a80: 70%
0 of 32752 at 0x60348a70: 71%
0 of 32752 at 0x60350a60: 72%
0 of 32752 at 0x60358a50: 73%
0 of 32752 at 0x60360a40: 73%
0 of 32752 at 0x60368a30: 74%
0 of 32752 at 0x60370a20: 75%
0 of 32752 at 0x60378a10: 76%
0 of 32752 at 0x60380a00: 77%
0 of 32752 at 0x603889f0: 77%
0 of 32752 at 0x603909e0: 78%
0 of 32752 at 0x603989d0: 79%
0 of 32752 at 0x603a09c0: 80%
0 of 32752 at 0x603a89b0: 81%
0 of 32752 at 0x603b09a0: 81%
0 of 32752 at 0x603b8990: 82%
0 of 32752 at 0x603c0980: 83%
0 of 32752 at 0x603c8970: 84%
0 of 32752 at 0x603d0960: 85%
0 of 32752 at 0x603d8950: 85%
0 of 32752 at 0x603e0940: 86%
0 of 32752 at 0x603e8930: 87%
0 of 32752 at 0x603f0920: 88%
0 of 32752 at 0x603f8910: 89%
0 of 32752 at 0x60400900: 90%
0 of 32752 at 0x604088f0: 90%
0 of 32752 at 0x604108e0: 91%
0 of 32752 at 0x604188d0: 92%
0 of 32752 at 0x604208c0: 93%
0 of 32752 at 0x604288b0: 94%
0 of 32752 at 0x604308a0: 94%
0 of 32752 at 0x60438890: 95%
0 of 32752 at 0x60440880: 96%
0 of 32752 at 0x60448870: 97%
0 of 32752 at 0x60450860: 98%
0 of 32752 at 0x60458850: 98%
0 of 14300 at 0x60460840: 99%
Finished: 99%
info: Cortex_R5_0: Writing 1 chunk at offset 0x81000
info: Cortex_R5_0: Writing 2 chunk at offset 0x91000
info: Cortex_R5_0: Writing 3 chunk at offset 0xa1000
info: Cortex_R5_0: Writing 4 chunk at offset 0xb1000
info: Cortex_R5_0: Writing 5 chunk at offset 0xc1000
info: Cortex_R5_0: Writing 6 chunk at offset 0xd1000
info: Cortex_R5_0: Writing 7 chunk at offset 0xe1000
info: Cortex_R5_0: Writing 8 chunk at offset 0xf1000
info: Cortex_R5_0: Writing 9 chunk at offset 0x101000
info: Cortex_R5_0: Writing 10 chunk at offset 0x111000
info: Cortex_R5_0: Writing 11 chunk at offset 0x121000
info: Cortex_R5_0: Writing 12 chunk at offset 0x131000
info: Cortex_R5_0: Writing 13 chunk at offset 0x141000
info: Cortex_R5_0: Writing 14 chunk at offset 0x151000
info: Cortex_R5_0: Writing 15 chunk at offset 0x161000
info: Cortex_R5_0: Writing 16 chunk at offset 0x171000
info: Cortex_R5_0: Writing 17 chunk at offset 0x181000
info: Cortex_R5_0: Writing 18 chunk at offset 0x191000
info: Cortex_R5_0: Writing 19 chunk at offset 0x1a1000
info: Cortex_R5_0: Writing 20 chunk at offset 0x1b1000
info: Cortex_R5_0: Writing 21 chunk at offset 0x1c1000
info: Cortex_R5_0: Writing 22 chunk at offset 0x1d1000
info: Cortex_R5_0: Writing 23 chunk at offset 0x1e1000
info: Cortex_R5_0: Writing 24 chunk at offset 0x1f1000
info: Cortex_R5_0: Writing 25 chunk at offset 0x201000
info: Cortex_R5_0: Writing 26 chunk at offset 0x211000
info: Cortex_R5_0: Writing 27 chunk at offset 0x221000
info: Cortex_R5_0: Writing 28 chunk at offset 0x231000
info: Cortex_R5_0: Writing 29 chunk at offset 0x241000
info: Cortex_R5_0: Writing 30 chunk at offset 0x251000
info: Cortex_R5_0: Writing 31 chunk at offset 0x261000
info: Cortex_R5_0: Writing 32 chunk at offset 0x271000
info: Cortex_R5_0: Writing 33 chunk at offset 0x281000
info: Cortex_R5_0: Writing 34 chunk at offset 0x291000
info: Cortex_R5_0: Writing 35 chunk at offset 0x2a1000
info: Cortex_R5_0: Writing 36 chunk at offset 0x2b1000
info: Cortex_R5_0: Writing 37 chunk at offset 0x2c1000
info: Cortex_R5_0: Writing 38 chunk at offset 0x2d1000
info: Cortex_R5_0: Writing 39 chunk at offset 0x2e1000
info: Cortex_R5_0: Writing 40 chunk at offset 0x2f1000
info: Cortex_R5_0: Writing 41 chunk at offset 0x301000
info: Cortex_R5_0: Writing 42 chunk at offset 0x311000
info: Cortex_R5_0: Writing 43 chunk at offset 0x321000
info: Cortex_R5_0: Writing 44 chunk at offset 0x331000
info: Cortex_R5_0: Writing 45 chunk at offset 0x341000
info: Cortex_R5_0: Writing 46 chunk at offset 0x351000
info: Cortex_R5_0: Writing 47 chunk at offset 0x361000
info: Cortex_R5_0: Writing 48 chunk at offset 0x371000
info: Cortex_R5_0: Writing 49 chunk at offset 0x381000
info: Cortex_R5_0: Writing 50 chunk at offset 0x391000
info: Cortex_R5_0: Writing 51 chunk at offset 0x3a1000
info: Cortex_R5_0: Writing 52 chunk at offset 0x3b1000
info: Cortex_R5_0: Writing 53 chunk at offset 0x3c1000
info: Cortex_R5_0: Writing 54 chunk at offset 0x3d1000
info: Cortex_R5_0: Writing 55 chunk at offset 0x3e1000
info: Cortex_R5_0: Writing 56 chunk at offset 0x3f1000
info: Cortex_R5_0: Writing 57 chunk at offset 0x401000
error: Cortex_R5_0: Run failed...
error: Cortex_R5_0: Trouble Removing Breakpoint with the Action "Remain Halted" at 0x7000c3a8: (Error -1066 @ 0x7000C3A8) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 20.0.0.3298)
error: Cortex_R5_0: File Loader: Failed to terminate flash programming: Timed out waiting for target to halt while executing flasher_jtag_uniflash_am263px-lp_r5fss0-0_nortos_ti-arm-clang.out
Failed: File: HWCAPP/user_files/images/myprogram.appimage: Load failed.

C:\Users\*\Downloads\test_bat\test_bat>
C:\Users\*\Downloads\test_bat\test_bat>test_bat.bat

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.
Please Wait...

Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
Cortex_R5_0: GEL Output:
OSPI - 8S Functional Boot Mode
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000101
Cortex_R5_0: GEL Output: r5fss1 = 0x00000100
Cortex_R5_0: GEL Output:
R5FSS0 is in Lockstep mode
Cortex_R5_0: GEL Output:
R5FSS1 is in Lockstep mode
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:

*** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output:

***R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

info: Cortex_R5_0: AM263Px_ZCZ_C
info: Cortex_R5_0: Board Selected : LP
info: Cortex_R5_0: Part Selected : Standard
Loading Program: SBL/user_files/images/loader.tiimage
Preparing ...
0 of 32752 at 0x60000000
0 of 32752 at 0x60007ff0: 14%
0 of 32752 at 0x6000ffe0: 29%
0 of 32752 at 0x60017fd0: 43%
0 of 32752 at 0x6001ffc0: 58%
0 of 32752 at 0x60027fb0: 72%
0 of 28236 at 0x6002ffa0: 87%
Finished: 87%
info: Cortex_R5_0: Writing 1 chunk at offset 0x0
info: Cortex_R5_0: Writing 2 chunk at offset 0x10000
info: Cortex_R5_0: Writing 3 chunk at offset 0x20000
info: Cortex_R5_0: Writing 4 chunk at offset 0x30000
Setting PC to entry point.: 87%
Verifying Program: SBL/user_files/images/loader.tiimage
Preparing ...
0 of 32752 at 0x60000000
0 of 32752 at 0x60007ff0: 14%
0 of 32752 at 0x6000ffe0: 29%
0 of 32752 at 0x60017fd0: 43%
0 of 32752 at 0x6001ffc0: 58%
0 of 32752 at 0x60027fb0: 72%
0 of 28236 at 0x6002ffa0: 87%
Finished: 87%
info: Cortex_R5_0: Program verification successful for SBL/user_files/images/loader.tiimage
Success
Executing default command:
> dslite --mode flash -c HWCAPP/user_files/configs/AM263Px_ZCZ_C.ccxml -l HWCAPP/user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -e -f -v "HWCAPP/user_files/images/myprogram.appimage,0x60081000"

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.
Please Wait...

Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
Cortex_R5_0: GEL Output:
OSPI - 8S Functional Boot Mode
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
Cortex_R5_0: GEL Output:
R5FSS0 is in Dual-Core mode
Cortex_R5_0: GEL Output:
R5FSS1 is in Dual-Core mode
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:

*** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output:

***R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

info: Cortex_R5_0: AM263Px_ZCZ_C
info: Cortex_R5_0: Board Selected : LP
info: Cortex_R5_0: Part Selected : Standard
Loading Program: HWCAPP/user_files/images/myprogram.appimage
Preparing ...
0 of 32752 at 0x60081000
0 of 32752 at 0x60088ff0
0 of 32752 at 0x60090fe0: 1%
0 of 32752 at 0x60098fd0: 2%
0 of 32752 at 0x600a0fc0: 3%
0 of 32752 at 0x600a8fb0: 4%
0 of 32752 at 0x600b0fa0: 4%
0 of 32752 at 0x600b8f90: 5%
0 of 32752 at 0x600c0f80: 6%
0 of 32752 at 0x600c8f70: 7%
0 of 32752 at 0x600d0f60: 8%
0 of 32752 at 0x600d8f50: 8%
0 of 32752 at 0x600e0f40: 9%
0 of 32752 at 0x600e8f30: 10%
0 of 32752 at 0x600f0f20: 11%
0 of 32752 at 0x600f8f10: 12%
0 of 32752 at 0x60100f00: 12%
0 of 32752 at 0x60108ef0: 13%
0 of 32752 at 0x60110ee0: 14%
0 of 32752 at 0x60118ed0: 15%
0 of 32752 at 0x60120ec0: 16%
0 of 32752 at 0x60128eb0: 16%
0 of 32752 at 0x60130ea0: 17%
0 of 32752 at 0x60138e90: 18%
0 of 32752 at 0x60140e80: 19%
0 of 32752 at 0x60148e70: 20%
0 of 32752 at 0x60150e60: 20%
0 of 32752 at 0x60158e50: 21%
0 of 32752 at 0x60160e40: 22%
0 of 32752 at 0x60168e30: 23%
0 of 32752 at 0x60170e20: 24%
0 of 32752 at 0x60178e10: 24%
0 of 32752 at 0x60180e00: 25%
0 of 32752 at 0x60188df0: 26%
0 of 32752 at 0x60190de0: 27%
0 of 32752 at 0x60198dd0: 28%
0 of 32752 at 0x601a0dc0: 28%
0 of 32752 at 0x601a8db0: 29%
0 of 32752 at 0x601b0da0: 30%
0 of 32752 at 0x601b8d90: 31%
0 of 32752 at 0x601c0d80: 32%
0 of 32752 at 0x601c8d70: 32%
0 of 32752 at 0x601d0d60: 33%
0 of 32752 at 0x601d8d50: 34%
0 of 32752 at 0x601e0d40: 35%
0 of 32752 at 0x601e8d30: 36%
0 of 32752 at 0x601f0d20: 36%
0 of 32752 at 0x601f8d10: 37%
0 of 32752 at 0x60200d00: 38%
0 of 32752 at 0x60208cf0: 39%
0 of 32752 at 0x60210ce0: 40%
0 of 32752 at 0x60218cd0: 40%
0 of 32752 at 0x60220cc0: 41%
0 of 32752 at 0x60228cb0: 42%
0 of 32752 at 0x60230ca0: 43%
0 of 32752 at 0x60238c90: 44%
0 of 32752 at 0x60240c80: 45%
0 of 32752 at 0x60248c70: 45%
0 of 32752 at 0x60250c60: 46%
0 of 32752 at 0x60258c50: 47%
0 of 32752 at 0x60260c40: 48%
0 of 32752 at 0x60268c30: 49%
0 of 32752 at 0x60270c20: 49%
0 of 32752 at 0x60278c10: 50%
0 of 32752 at 0x60280c00: 51%
0 of 32752 at 0x60288bf0: 52%
0 of 32752 at 0x60290be0: 53%
0 of 32752 at 0x60298bd0: 53%
0 of 32752 at 0x602a0bc0: 54%
0 of 32752 at 0x602a8bb0: 55%
0 of 32752 at 0x602b0ba0: 56%
0 of 32752 at 0x602b8b90: 57%
0 of 32752 at 0x602c0b80: 57%
0 of 32752 at 0x602c8b70: 58%
0 of 32752 at 0x602d0b60: 59%
0 of 32752 at 0x602d8b50: 60%
0 of 32752 at 0x602e0b40: 61%
0 of 32752 at 0x602e8b30: 61%
0 of 32752 at 0x602f0b20: 62%
0 of 32752 at 0x602f8b10: 63%
0 of 32752 at 0x60300b00: 64%
0 of 32752 at 0x60308af0: 65%
0 of 32752 at 0x60310ae0: 65%
0 of 32752 at 0x60318ad0: 66%
0 of 32752 at 0x60320ac0: 67%
0 of 32752 at 0x60328ab0: 68%
0 of 32752 at 0x60330aa0: 69%
0 of 32752 at 0x60338a90: 69%
0 of 32752 at 0x60340a80: 70%
0 of 32752 at 0x60348a70: 71%
0 of 32752 at 0x60350a60: 72%
0 of 32752 at 0x60358a50: 73%
0 of 32752 at 0x60360a40: 73%
0 of 32752 at 0x60368a30: 74%
0 of 32752 at 0x60370a20: 75%
0 of 32752 at 0x60378a10: 76%
0 of 32752 at 0x60380a00: 77%
0 of 32752 at 0x603889f0: 77%
0 of 32752 at 0x603909e0: 78%
0 of 32752 at 0x603989d0: 79%
0 of 32752 at 0x603a09c0: 80%
0 of 32752 at 0x603a89b0: 81%
0 of 32752 at 0x603b09a0: 81%
0 of 32752 at 0x603b8990: 82%
0 of 32752 at 0x603c0980: 83%
0 of 32752 at 0x603c8970: 84%
0 of 32752 at 0x603d0960: 85%
0 of 32752 at 0x603d8950: 85%
0 of 32752 at 0x603e0940: 86%
0 of 32752 at 0x603e8930: 87%
0 of 32752 at 0x603f0920: 88%
0 of 32752 at 0x603f8910: 89%
0 of 32752 at 0x60400900: 90%
0 of 32752 at 0x604088f0: 90%
0 of 32752 at 0x604108e0: 91%
0 of 32752 at 0x604188d0: 92%
0 of 32752 at 0x604208c0: 93%
0 of 32752 at 0x604288b0: 94%
0 of 32752 at 0x604308a0: 94%
0 of 32752 at 0x60438890: 95%
0 of 32752 at 0x60440880: 96%
0 of 32752 at 0x60448870: 97%
0 of 32752 at 0x60450860: 98%
0 of 32752 at 0x60458850: 98%
0 of 14300 at 0x60460840: 99%
Finished: 99%
info: Cortex_R5_0: Writing 1 chunk at offset 0x81000
info: Cortex_R5_0: Writing 2 chunk at offset 0x91000
info: Cortex_R5_0: Writing 3 chunk at offset 0xa1000
info: Cortex_R5_0: Writing 4 chunk at offset 0xb1000
info: Cortex_R5_0: Writing 5 chunk at offset 0xc1000
info: Cortex_R5_0: Writing 6 chunk at offset 0xd1000
info: Cortex_R5_0: Writing 7 chunk at offset 0xe1000
info: Cortex_R5_0: Writing 8 chunk at offset 0xf1000
info: Cortex_R5_0: Writing 9 chunk at offset 0x101000
info: Cortex_R5_0: Writing 10 chunk at offset 0x111000
info: Cortex_R5_0: Writing 11 chunk at offset 0x121000
info: Cortex_R5_0: Writing 12 chunk at offset 0x131000
info: Cortex_R5_0: Writing 13 chunk at offset 0x141000
info: Cortex_R5_0: Writing 14 chunk at offset 0x151000
info: Cortex_R5_0: Writing 15 chunk at offset 0x161000
info: Cortex_R5_0: Writing 16 chunk at offset 0x171000
info: Cortex_R5_0: Writing 17 chunk at offset 0x181000
info: Cortex_R5_0: Writing 18 chunk at offset 0x191000
info: Cortex_R5_0: Writing 19 chunk at offset 0x1a1000
info: Cortex_R5_0: Writing 20 chunk at offset 0x1b1000
info: Cortex_R5_0: Writing 21 chunk at offset 0x1c1000
info: Cortex_R5_0: Writing 22 chunk at offset 0x1d1000
info: Cortex_R5_0: Writing 23 chunk at offset 0x1e1000
info: Cortex_R5_0: Writing 24 chunk at offset 0x1f1000
info: Cortex_R5_0: Writing 25 chunk at offset 0x201000
info: Cortex_R5_0: Writing 26 chunk at offset 0x211000
info: Cortex_R5_0: Writing 27 chunk at offset 0x221000
info: Cortex_R5_0: Writing 28 chunk at offset 0x231000
info: Cortex_R5_0: Writing 29 chunk at offset 0x241000
info: Cortex_R5_0: Writing 30 chunk at offset 0x251000
info: Cortex_R5_0: Writing 31 chunk at offset 0x261000
info: Cortex_R5_0: Writing 32 chunk at offset 0x271000
info: Cortex_R5_0: Writing 33 chunk at offset 0x281000
info: Cortex_R5_0: Writing 34 chunk at offset 0x291000
info: Cortex_R5_0: Writing 35 chunk at offset 0x2a1000
info: Cortex_R5_0: Writing 36 chunk at offset 0x2b1000
info: Cortex_R5_0: Writing 37 chunk at offset 0x2c1000
info: Cortex_R5_0: Writing 38 chunk at offset 0x2d1000
info: Cortex_R5_0: Writing 39 chunk at offset 0x2e1000
info: Cortex_R5_0: Writing 40 chunk at offset 0x2f1000
info: Cortex_R5_0: Writing 41 chunk at offset 0x301000
info: Cortex_R5_0: Writing 42 chunk at offset 0x311000
info: Cortex_R5_0: Writing 43 chunk at offset 0x321000
info: Cortex_R5_0: Writing 44 chunk at offset 0x331000
info: Cortex_R5_0: Writing 45 chunk at offset 0x341000
info: Cortex_R5_0: Writing 46 chunk at offset 0x351000
info: Cortex_R5_0: Writing 47 chunk at offset 0x361000
info: Cortex_R5_0: Writing 48 chunk at offset 0x371000
info: Cortex_R5_0: Writing 49 chunk at offset 0x381000
info: Cortex_R5_0: Writing 50 chunk at offset 0x391000
info: Cortex_R5_0: Writing 51 chunk at offset 0x3a1000
info: Cortex_R5_0: Writing 52 chunk at offset 0x3b1000
info: Cortex_R5_0: Writing 53 chunk at offset 0x3c1000
info: Cortex_R5_0: Writing 54 chunk at offset 0x3d1000
info: Cortex_R5_0: Writing 55 chunk at offset 0x3e1000
info: Cortex_R5_0: Writing 56 chunk at offset 0x3f1000
info: Cortex_R5_0: Writing 57 chunk at offset 0x401000
info: Cortex_R5_0: Writing 58 chunk at offset 0x411000
info: Cortex_R5_0: Writing 59 chunk at offset 0x421000
info: Cortex_R5_0: Writing 60 chunk at offset 0x431000
info: Cortex_R5_0: Writing 61 chunk at offset 0x441000
info: Cortex_R5_0: Writing 62 chunk at offset 0x451000
info: Cortex_R5_0: Writing 63 chunk at offset 0x461000
error: Cortex_R5_0: Error Code 40000001
error: Cortex_R5_0: Error Loading the data...
error: Cortex_R5_0: Run failed...
error: Cortex_R5_0: File Loader: Failed to terminate flash programming: Algorithm indicated it failed to flash the data
Failed: File: HWCAPP/user_files/images/myprogram.appimage: Load failed.

2 months ago

0 Aswin P 2 months ago

TI__Genius 10511 points

Hi,

Let me loop the subject experts.

Thanks

Aswin

0 Aswin Sankar 2 months ago in reply to Aswin P

TI__Genius 9595 points

Hi,

Apologies for the delay in response.

Can you confirm if you are seeing the issue with the latest uniflash tool?

Also may I know if there is some application actively running in the device while the flashing process is happening? Typically this kind of logs come when the debugger is unable to interrupt the core, stop its execuction and exert its breakpoint.

Would also appreciate if you can test using the GUI tool once the error is reproduced.

Thanks & Regards,

Aswin

0 ATSUKI IMADA 2 months ago

Prodigy 80 points

Hi Aswin,

Thank you for your response.

Due to the constraints of the SDK version currently in use, I believe it would be difficult for us to change the UniFlash version.

However, if the latest version of UniFlash supports selecting an .appimage file when using the Standalone CLI, then upgrading to the latest version may be possible.

Also, in this verification, we changed the boot mode to DevBoot mode and performed a flash erase on the board before attempting to reprogram it using UniFlash. Therefore, I do not believe that any application was running on the device during the flashing process.

In addition, the same log messages were observed when using both the GUI version and the CLI version of UniFlash.

As this is a critical and time-sensitive issue for our project, I would greatly appreciate it if you could provide your feedback at your earliest convenience.

Thank you for your support.

Best regards,

Imada

0 Aswin Sankar 2 months ago in reply to ATSUKI IMADA

TI__Genius 9595 points

Hi Imada-San,

Let me check this on my side and get back to you

Thanks & Regards,

Aswin

0 Aswin Sankar 2 months ago in reply to Aswin Sankar

TI__Genius 9595 points

Hi Imada-San,

App image works with the latest uniflash. I tested the viability using 9.6.0. Please use the below commands.

Command to erase
---------------------------------
./dslite.sh --mode flash --config="/home/ti/CCSTargetConfigurations/am263px-lp.ccxml" -n 0 -s CustomFlashEnable=1 -s FlasherCustomPath="/home/ti/am263px/mcu+sdk/mcu_plus_sdk_am263px_26_00_00_06/tools/flasher/jtag_uniflash/am263px-lp/r5fss0-0_nortos/ti-arm-clang" -s FlasherCustomName="flasher_jtag_uniflash.release.out" -b EraseAll

Coomand to flash SBL
--------------------------------
./dslite.sh --mode flash --config="/home/ti/CCSTargetConfigurations/am263px-lp.ccxml" -n 0 -s CustomFlashEnable=1 -s FlasherCustomPath="/home/ti/am263px/mcu+sdk/mcu_plus_sdk_am263px_26_00_00_06/tools/flasher/jtag_uniflash/am263px-lp/r5fss0-0_nortos/ti-arm-clang" -s FlasherCustomName="flasher_jtag_uniflash.release.out" --flash "/home/ti/am263px/mcu+sdk/mcu_plus_sdk_am263px_10_02_00_15/tools/boot/sbl_prebuilt/am263px-lp/sbl_ospi.debug.tiimage,0x60000000"

Command to flash App
-------------------------------
./dslite.sh --mode flash --config="/home/ti/CCSTargetConfigurations/am263px-lp.ccxml" -n 0 -s CustomFlashEnable=1 -s FlasherCustomPath="/home/ti/am263px/mcu+sdk/mcu_plus_sdk_am263px_26_00_00_06/tools/flasher/jtag_uniflash/am263px-lp/r5fss0-0_nortos/ti-arm-clang" -s FlasherCustomName="flasher_jtag_uniflash.release.out" --flash "/home/ti/am263px/mcu+sdk/mcu_plus_sdk_am263px_10_02_00_15/examples/drivers/uart/uart_echo/am263px-lp/r5fss0-0_freertos/ti-arm-clang/uart_echo.release.appimage,0x60081000"

Please replace the paths accordingly.

Please do test using this version let me know of the result.

Thanks & Regards,

Aswin

0 ATSUKI IMADA 2 months ago in reply to Aswin Sankar

Prodigy 80 points

Dear Aswin,

Thank you for your reply.

I changed the UniFlash version to 9.6.0 and generated a batch file using the Standalone Command Line interface for testing.

As a result, I modified the command you provided. However, when flashing the SBL image, the log that normally shows the verification result after the programming process completes is no longer displayed.

SBL Log

C:\Users\userID\Downloads\uniflash_SBL>dslite-Cortex_R5_0.bat --mode flash --config="./user_files/configs/AM263Px_ZCZ_C.ccxml" -n 0 -s CustomFlashEnable=1 -s FlasherCustomPath="C:/ti" -s FlasherCustomName="flasher_jtag_uniflash_am263px-lp_r5fss0-0_nortos_ti-arm-clang.out" --flash "./user_files/images/SBL.tiimage,0x60000000"
Executing the following command:
> "C:\Users\userID\Downloads\uniflash_SBL\ccs_base\DebugServer\bin\DSLite" flash --config="./user_files/configs/AM263Px_ZCZ_C.ccxml" -n 0 -s CustomFlashEnable=1 -s FlasherCustomPath="C:/ti" -s FlasherCustomName="flasher_jtag_uniflash_am263px-lp_r5fss0-0_nortos_ti-arm-clang.out" --flash "./user_files/images/SBL.tiimage,0x60000000"

For more details and examples, please visit software-dl.ti.com/.../latest_qsguide.html

Cortex_R5_0: GEL Output: Gel files loading Complete
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.
Please Wait...


Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B
Cortex_R5_0: GEL Output: Dev Boot Mode
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
Cortex_R5_0: GEL Output:

 *** Enabling Peripheral Clocks ***
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: Enabling OSPI Clocks
Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
Cortex_R5_0: GEL Output: Enabling I2C Clocks
Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling TRACE Clocks
Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
Cortex_R5_0: GEL Output: Enabling CPTS Clocks
Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
Cortex_R5_0: GEL Output:

 ***All IP Clocks are Enabled***

info: Cortex_R5_0: AM263Px_ZCZ_C
info: Cortex_R5_0: Board Selected : LP
info: Cortex_R5_0: Part Selected : Standard
Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL on program load.
info: Cortex_R5_0: Writing 1 chunk at offset 0x0
info: Cortex_R5_0: Writing 2 chunk at offset 0x10000
info: Cortex_R5_0: Writing 3 chunk at offset 0x20000
info: Cortex_R5_0: Writing 4 chunk at offset 0x30000

In addition, when flashing the APPIMAGE, the write progress is displayed as expected, but I still encounter the same error as before:

error: Cortex_R5_0: File Loader: Failed to terminate flash programming:
Algorithm indicated it failed to flash the data

APPIMAGE Log


C:\Users\userID\Downloads\uniflash_HWCAPP>dslite-Cortex_R5_0.bat --mode flash --config="./user_files/configs/AM263Px_ZCZ_C.ccxml" -n 0 -s CustomFlashEnable=1 -s FlasherCustomPath="C:/ti" -s FlasherCustomName="flasher_jtag_uniflash_am263px-lp_r5fss0-0_nortos_ti-arm-clang.out" --flash "./user_files/images/myAPP.appimage,0x60081000"
Executing the following command:
> "C:\Users\userID\Downloads\uniflash_HWCAPP\ccs_base\DebugServer\bin\DSLite" flash --config="./user_files/configs/AM263Px_ZCZ_C.ccxml" -n 0 -s CustomFlashEnable=1 -s FlasherCustomPath="C:/ti" -s FlasherCustomName="flasher_jtag_uniflash_am263px-lp_r5fss0-0_nortos_ti-arm-clang.out" --flash "./user_files/images/myAPP.appimage,0x60081000"

For more details and examples, please visit software-dl.ti.com/.../latest_qsguide.html

Cortex_R5_0: GEL Output: Gel files loading Complete
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.
Please Wait...


Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B
Cortex_R5_0: GEL Output: Dev Boot Mode
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
Cortex_R5_0: GEL Output:

 *** Enabling Peripheral Clocks ***
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: Enabling OSPI Clocks
Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
Cortex_R5_0: GEL Output: Enabling I2C Clocks
Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling TRACE Clocks
Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
Cortex_R5_0: GEL Output: Enabling CPTS Clocks
Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
Cortex_R5_0: GEL Output:

 ***All IP Clocks are Enabled***

info: Cortex_R5_0: AM263Px_ZCZ_C
info: Cortex_R5_0: Board Selected : LP
info: Cortex_R5_0: Part Selected : Standard
Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL on program load.
info: Cortex_R5_0: Writing 1 chunk at offset 0x81000
info: Cortex_R5_0: Writing 2 chunk at offset 0x91000
info: Cortex_R5_0: Writing 3 chunk at offset 0xa1000
info: Cortex_R5_0: Writing 4 chunk at offset 0xb1000
info: Cortex_R5_0: Writing 5 chunk at offset 0xc1000
info: Cortex_R5_0: Writing 6 chunk at offset 0xd1000
info: Cortex_R5_0: Writing 7 chunk at offset 0xe1000
info: Cortex_R5_0: Writing 8 chunk at offset 0xf1000
info: Cortex_R5_0: Writing 9 chunk at offset 0x101000
info: Cortex_R5_0: Writing 10 chunk at offset 0x111000
info: Cortex_R5_0: Writing 11 chunk at offset 0x121000
info: Cortex_R5_0: Writing 12 chunk at offset 0x131000
info: Cortex_R5_0: Writing 13 chunk at offset 0x141000
info: Cortex_R5_0: Writing 14 chunk at offset 0x151000
info: Cortex_R5_0: Writing 15 chunk at offset 0x161000
info: Cortex_R5_0: Writing 16 chunk at offset 0x171000
info: Cortex_R5_0: Writing 17 chunk at offset 0x181000
info: Cortex_R5_0: Writing 18 chunk at offset 0x191000
info: Cortex_R5_0: Writing 19 chunk at offset 0x1a1000
info: Cortex_R5_0: Writing 20 chunk at offset 0x1b1000
info: Cortex_R5_0: Writing 21 chunk at offset 0x1c1000
info: Cortex_R5_0: Writing 22 chunk at offset 0x1d1000
info: Cortex_R5_0: Writing 23 chunk at offset 0x1e1000
info: Cortex_R5_0: Writing 24 chunk at offset 0x1f1000
info: Cortex_R5_0: Writing 25 chunk at offset 0x201000
info: Cortex_R5_0: Writing 26 chunk at offset 0x211000
info: Cortex_R5_0: Writing 27 chunk at offset 0x221000
info: Cortex_R5_0: Writing 28 chunk at offset 0x231000
info: Cortex_R5_0: Writing 29 chunk at offset 0x241000
info: Cortex_R5_0: Writing 30 chunk at offset 0x251000
info: Cortex_R5_0: Writing 31 chunk at offset 0x261000
info: Cortex_R5_0: Writing 32 chunk at offset 0x271000
info: Cortex_R5_0: Writing 33 chunk at offset 0x281000
info: Cortex_R5_0: Writing 34 chunk at offset 0x291000
info: Cortex_R5_0: Writing 35 chunk at offset 0x2a1000
info: Cortex_R5_0: Writing 36 chunk at offset 0x2b1000
info: Cortex_R5_0: Writing 37 chunk at offset 0x2c1000
info: Cortex_R5_0: Writing 38 chunk at offset 0x2d1000
info: Cortex_R5_0: Writing 39 chunk at offset 0x2e1000
info: Cortex_R5_0: Writing 40 chunk at offset 0x2f1000
info: Cortex_R5_0: Writing 41 chunk at offset 0x301000
info: Cortex_R5_0: Writing 42 chunk at offset 0x311000
info: Cortex_R5_0: Writing 43 chunk at offset 0x321000
info: Cortex_R5_0: Writing 44 chunk at offset 0x331000
info: Cortex_R5_0: Writing 45 chunk at offset 0x341000
info: Cortex_R5_0: Writing 46 chunk at offset 0x351000
info: Cortex_R5_0: Writing 47 chunk at offset 0x361000
info: Cortex_R5_0: Writing 48 chunk at offset 0x371000
info: Cortex_R5_0: Writing 49 chunk at offset 0x381000
info: Cortex_R5_0: Writing 50 chunk at offset 0x391000
info: Cortex_R5_0: Writing 51 chunk at offset 0x3a1000
info: Cortex_R5_0: Writing 52 chunk at offset 0x3b1000
info: Cortex_R5_0: Writing 53 chunk at offset 0x3c1000
info: Cortex_R5_0: Writing 54 chunk at offset 0x3d1000
info: Cortex_R5_0: Writing 55 chunk at offset 0x3e1000
info: Cortex_R5_0: Writing 56 chunk at offset 0x3f1000
info: Cortex_R5_0: Writing 57 chunk at offset 0x401000
info: Cortex_R5_0: Writing 58 chunk at offset 0x411000
info: Cortex_R5_0: Writing 59 chunk at offset 0x421000
info: Cortex_R5_0: Writing 60 chunk at offset 0x431000
info: Cortex_R5_0: Writing 61 chunk at offset 0x441000
info: Cortex_R5_0: Writing 62 chunk at offset 0x451000
info: Cortex_R5_0: Writing 63 chunk at offset 0x461000
error: Cortex_R5_0: Error Code 40000001
error: Cortex_R5_0: Error Loading the data...
error: Cortex_R5_0: Run failed...
error: Cortex_R5_0: File Loader: Failed to terminate flash programming: Algorithm indicated it failed to flash the data
Failed: File: ./user_files/images/myAPP.appimage: Load failed.

I would appreciate it if you could provide any suggestions or possible solutions for this issue.

Best regards,

Imada

0 Aswin Sankar 2 months ago in reply to ATSUKI IMADA

TI__Genius 9595 points

Hi Imada-San,

I could not get this issue. To reproduce this can you please provide me the size of the app image being flashed? Do you see any correlation between image size?

Is the issue always coming even with small images?

Thanks & Regards,
Aswin

0 ATSUKI IMADA 2 months ago in reply to Aswin Sankar

Prodigy 80 points

Hi Aswin,

I apologize for the delayed response.

Verification Environment

UniFlash 9.3.0
IS25LX128 (using a custom flasher)

I would like to report the file sizes for the case previously mentioned.

SBL

224,748 bytes

APPIMAGE

4,075,548 bytes

In addition, I tested using your sample code and would like to share the results below.

Please note that I restarted UniFlash before each programming attempt.

SBL(sbl_ospi_am263px-lp_r5fss0-0_nortos_ti-arm-clang.tiimage)

224,748 bytes
The same error occurred in all three attempts.

[2026/8/24 8:36:20] [ERROR] Cortex_R5_0: Error Code 40000001

[2026/8/24 8:36:20] [ERROR] Cortex_R5_0: Error Loading the data...

[2026/8/24 8:36:20] [ERROR] Cortex_R5_0: Run failed...

[2026/8/24 8:36:20] [ERROR] Cortex_R5_0: File Loader: Failed to terminate flash programming: Algorithm indicated it failed to flash the data

APPIMAGE(hello_world_am263px-lp_r5fss0-0_nortos_ti-arm-clang.appimage)

31,596 bytes
All three attempts completed successfully.

[2026/8/24 8:37:20] [SUCCESS] Program Load completed successfully.

Based on these results, the issue does not appear to be directly related to image size, since the relatively small SBL image consistently fails while the APPIMAGE is programmed successfully.

Please let me know if any additional information is needed.

Best regards,

imada

0 ATSUKI IMADA 2 months ago

Prodigy 80 points

Hi Aswin,

I have already provided the information requested in your previous inquiry. Could you please review my response as soon as possible and let me know your findings?

I would appreciate your prompt attention to this matter.

Best regards,
Imada

0 Aswin Sankar 2 months ago in reply to ATSUKI IMADA

TI__Genius 9595 points

Hi Imada-San,

Apologies for the delay, I was OOO last week. Let me check this and get back to you asap

Thanks & Regards,

Aswin

0 Aswin Sankar 1 month ago in reply to Aswin Sankar

TI__Genius 9595 points

Hi Imada-San,

I have one question regarding the application size. I see it is 3.88 MB, but the device lacks this much amount of RAM. Can you confirm if XIP is used as we do not have this much OCSRAM. The device has 6 banks of 512 KB each only

Thanks & Regards,

Aswin

0 ATSUKI IMADA 1 month ago in reply to Aswin Sankar

Prodigy 80 points

Hi Aswin,

Sorry for the delayed response.

Regarding your question:

1. We are not using XIP at this time. However, there is a possibility that we may use XIP after upgrading to SDK11 in the future.

2. The 3.88 MB app image size includes not only the program code but also other data/files contained in the image. The maximum program size itself is designed to be 2044 KB.

Therefore, the 3.88 MB size does not mean that the entire image is loaded into OCSRAM.

Thanks & Regards,
Imada

0 Aswin Sankar 1 month ago in reply to ATSUKI IMADA

TI__Genius 9595 points

Hi Imada-San,

I could see a similar issue while flashing some huge files via UniFlash GUI tool.

Attaching the log here, Looping in experts from UniFlash tool to help reason the issue.

Thanks & Regards,

Aswin

0 ATSUKI IMADA 1 month ago in reply to Aswin Sankar

Prodigy 80 points

Hi Aswin,

Thank you for your update.

Although you were able to reproduce a flashing issue on your side, the error reported in your log appears to be different from the one we are seeing.

Your log:

[ERROR] Cortex_R5_0: Run failed...
[ERROR] Cortex_R5_0: File Loader: Memory write failed:
Timed out waiting for target to halt while executing flasher_jtag_uniflash_am261x-som_r5fss0-0_nortos_ti-arm-clang.out

Our log:

error: Cortex_R5_0: Run failed...
error: Cortex_R5_0: File Loader: Failed to terminate flash programming:
Algorithm indicated it failed to flash the data

In your case, UniFlash reports a "Memory write failed" error because it timed out while waiting for the target to halt during execution of the flasher. In contrast, our case reports "Failed to terminate flash programming" with the message "Algorithm indicated it failed to flash the data."

While the symptoms may appear similar, the failure point and underlying cause may be different.

In addition, I understand that your validation was performed on an AM261x device, whereas we are using an AM263Px device. Therefore, the difference in device type may also be a factor.

Could you please ask the UniFlash team to review whether these two errors are related or if they originate from different causes?

Best regards,

Imada

0 Ki 1 month ago in reply to ATSUKI IMADA

TI__Guru**** 486931 points

Imada-san,

Would it be possible to provide your standalone package? I don't need all the content in ccs_base so you can remove that. Since that folder is the biggest size, removing that should shrink the overall size a lot.

You can share privately to me using E2E private message.

Thank you,

0 ATSUKI IMADA 1 month ago

Prodigy 80 points

Hi Ki,

Thank you for your message.

I believe it should be possible to provide a standalone package. However, I have already generated a standalone package using the UniFlash GUI and tested programming with it, and I was able to reproduce the same error that we have been discussing.

On the other hand, I am not entirely sure which parts of ccs_base you require. Could you please let me know which specific components you need?

Also, would it be acceptable if I remove the programming files and other unnecessary files before sharing the package?

I would appreciate it if you could provide your feedback as soon as possible.

Thank you for your help.

Best regards,
Imada

0 ATSUKI IMADA 1 month ago in reply to ATSUKI IMADA

Prodigy 80 points

Hi Ki,

Hello.

I have made some additional progress in the investigation and would like to share the results.

I tried programming our application onto your LP-AM263P board in DevBoot mode using the default settings (i.e., without any custom flasher), and I observed the following log:

Although this result differs from what we see on our custom board, I wanted to share it for reference.

[2026/9/17 16:39:47] [INFO] Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL on program load.

[2026/9/17 16:39:49] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x0

[2026/9/17 16:40:01] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x81000

[2026/9/17 16:40:22] [ERROR] Cortex_R5_0: Run failed...

[2026/9/17 16:40:22] [ERROR] Cortex_R5_0: File Loader: Failed to terminate flash programming: Timed out waiting for target to halt while executing am263px_lp_flasher.out

Please let me know if this information is helpful.

Best regards,

Imada

0 Ki 1 month ago in reply to ATSUKI IMADA

TI__Guru**** 486931 points

ATSUKI IMADA said:
On the other hand, I am not entirely sure which parts of ccs_base you require.

I do not need anything from that folder. So you can omit that folder completely.I just need everything else except that folder.

ATSUKI IMADA said:
Also, would it be acceptable if I remove the programming files and other unnecessary files before sharing the package?

However, I would like everything else besides the ccs_base folder. This includes the entire user_files folder also.

0 ATSUKI IMADA 1 month ago in reply to Ki

Prodigy 80 points

Hi KI,

Sorry, I misread the previous chat.

To be honest, I do not think it is feasible to provide our program unless you can clearly explain what exactly you would like to investigate.

The reason is that even when we program the LP-AM263P with our software using UniFlash, we do not observe the same error that occurs on our custom board. Instead, a different error appears. Given the current situation, I do not think the issue will be reproducible in your environment.

If I had to point out a key difference, our custom board uses a 128 Mb EEPROM instead of the one used on the LP board, and we use a dedicated custom flasher.

In addition, the person who handled our previous support case stated that:

"This type of log occurs when the debugger interrupts the core, halts execution, and is unable to apply breakpoints."

At that time, if I remember correctly, we had erased the flash on our custom board and configured it for DevBoot mode during verification. Since no application should have been running in that state, could you explain why this issue would still occur?

Also, as a separate question, are there any limitations on program size when writing firmware using UniFlash?

For example, is there a restriction such as not being able to program images larger than 3 MB in a single operation?

Thank you for your support.

I would appreciate it if you could provide your response as soon as possible.

Best regards,

Imada

0 ATSUKI IMADA 1 month ago

Prodigy 80 points

Hi KI,

I hope you are doing well.

It has been quite some time since my last message, so I would like to follow up and ask if there have been any updates regarding this matter.

If possible, I would greatly appreciate receiving some kind of response at your earliest convenience.

Best regards,

Atsuki Imada

0 Ricky Lau 21 days ago in reply to ATSUKI IMADA

TI__Genius 13395 points

Hi Imada,

I'm very sorry for the late reply. Ki was away, and the thread was reassigned to me.

Due to the complexity of the issue, especially with the custom flasher and board, it is not easy to try to reproduce the issue.

We are internally discussing options to help debug this issue with you. We will get back to you as soon as possible with suggestions.

Thank you very much,

Ricky

0 ATSUKI IMADA 19 days ago

Prodigy 80 points

Hi Ricky,

Thank you for your update. We appreciate your continued support on this matter.

At the same time, this issue is quite critical for us, and we are hoping to have it resolved by around mid-November 2026.

Therefore, if there is anything that we can investigate or verify on our side to help with the debugging process,

I would appreciate it if you could let us know as early as possible. We look forward to your suggestions and continued support.

Best regards,

Imada

0 Ki 13 days ago in reply to Aswin Sankar

TI__Guru**** 486931 points

Aswin Sankar said:
I could see a similar issue while flashing some huge files via UniFlash GUI tool.

Aswin - it looks like you are running into the timeout issue mentioned in this thread:

RE: AM263P4-Q1: Uniflash Tool Issue while flashing the image

Can you see if increasing the timeout from UniFlash CLI resolves the issue in your case?

Regardless, the issue you ran into is different from the issue encountered by Imada-san. The issue from Imada-san appears to be a failure coming from the flash programmer specifically and not from the UniFlash tool.

Looks like there is an active internal discussion with engineering. We can continue discussion there.

0 ATSUKI IMADA 13 days ago

Prodigy 80 points

Hi Ki,

Thank you for your continued support.

As you suggested, I set the timeout value using the command-line argument when running DSLite. However, I confirmed that the same error still occurs even with the increased timeout value.

The log is shown below:

C:\Users\User\Downloads\test_bat_20260818\test_bat>test_bat.bat

C:\Users\User\Downloads\test_bat_20260818\test_bat>call ./SBL/dslite-Cortex_R5_0.bat
Executing default command:
> dslite --mode flash -c SBL/user_files/configs/AM263Px_ZCZ_C.ccxml -l SBL/user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -t 120 -e -f -v "SBL/user_files/images/MyProgram_LD_00_05_260703.tiimage,0x60000000"

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.
Please Wait...

Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B
Cortex_R5_0: GEL Output:
Dev Boot Mode
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
Cortex_R5_0: GEL Output:
R5FSS0 is in Dual-Core mode
Cortex_R5_0: GEL Output:
R5FSS1 is in Dual-Core mode
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:

*** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output:

***R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

info: Cortex_R5_0: AM263Px_ZCZ_C
info: Cortex_R5_0: Board Selected : LP
info: Cortex_R5_0: Part Selected : Standard
Loading Program: SBL/user_files/images/MyProgram_LD_00_05_260703.tiimage
Preparing ...
0 of 32752 at 0x60000000
0 of 32752 at 0x60007ff0: 14%
0 of 32752 at 0x6000ffe0: 29%
0 of 32752 at 0x60017fd0: 43%
0 of 32752 at 0x6001ffc0: 58%
0 of 32752 at 0x60027fb0: 72%
0 of 28236 at 0x6002ffa0: 87%
Finished: 87%
info: Cortex_R5_0: Writing 1 chunk at offset 0x0
info: Cortex_R5_0: Writing 2 chunk at offset 0x10000
info: Cortex_R5_0: Writing 3 chunk at offset 0x20000
info: Cortex_R5_0: Writing 4 chunk at offset 0x30000
Setting PC to entry point.: 87%
Verifying Program: SBL/user_files/images/MyProgram_LD_00_05_260703.tiimage
Preparing ...
0 of 32752 at 0x60000000
0 of 32752 at 0x60007ff0: 14%
0 of 32752 at 0x6000ffe0: 29%
0 of 32752 at 0x60017fd0: 43%
0 of 32752 at 0x6001ffc0: 58%
0 of 32752 at 0x60027fb0: 72%
0 of 28236 at 0x6002ffa0: 87%
Finished: 87%
info: Cortex_R5_0: Program verification successful for SBL/user_files/images/MyProgram_LD_00_05_260703.tiimage
Success
Executing default command:
> dslite --mode flash -c HWCAPP/user_files/configs/AM263Px_ZCZ_C.ccxml -l HWCAPP/user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -t 6000 -e -f -v "HWCAPP/user_files/images/MyProgram_HWC_0804_1.appimage,0x60081000"

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.
Please Wait...

Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B
Cortex_R5_0: GEL Output:
Dev Boot Mode
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
Cortex_R5_0: GEL Output:
R5FSS0 is in Dual-Core mode
Cortex_R5_0: GEL Output:
R5FSS1 is in Dual-Core mode
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:

*** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output:

***R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

info: Cortex_R5_0: AM263Px_ZCZ_C
info: Cortex_R5_0: Board Selected : LP
info: Cortex_R5_0: Part Selected : Standard
Loading Program: HWCAPP/user_files/images/MyProgram_HWC_0804_1.appimage
Preparing ...
0 of 32752 at 0x60081000
0 of 32752 at 0x60088ff0
0 of 32752 at 0x60090fe0: 1%
0 of 32752 at 0x60098fd0: 2%
0 of 32752 at 0x600a0fc0: 3%
0 of 32752 at 0x600a8fb0: 4%
0 of 32752 at 0x600b0fa0: 4%
0 of 32752 at 0x600b8f90: 5%
0 of 32752 at 0x600c0f80: 6%
0 of 32752 at 0x600c8f70: 7%
0 of 32752 at 0x600d0f60: 8%
0 of 32752 at 0x600d8f50: 8%
0 of 32752 at 0x600e0f40: 9%
0 of 32752 at 0x600e8f30: 10%
0 of 32752 at 0x600f0f20: 11%
0 of 32752 at 0x600f8f10: 12%
0 of 32752 at 0x60100f00: 12%
0 of 32752 at 0x60108ef0: 13%
0 of 32752 at 0x60110ee0: 14%
0 of 32752 at 0x60118ed0: 15%
0 of 32752 at 0x60120ec0: 16%
0 of 32752 at 0x60128eb0: 16%
0 of 32752 at 0x60130ea0: 17%
0 of 32752 at 0x60138e90: 18%
0 of 32752 at 0x60140e80: 19%
0 of 32752 at 0x60148e70: 20%
0 of 32752 at 0x60150e60: 20%
0 of 32752 at 0x60158e50: 21%
0 of 32752 at 0x60160e40: 22%
0 of 32752 at 0x60168e30: 23%
0 of 32752 at 0x60170e20: 24%
0 of 32752 at 0x60178e10: 24%
0 of 32752 at 0x60180e00: 25%
0 of 32752 at 0x60188df0: 26%
0 of 32752 at 0x60190de0: 27%
0 of 32752 at 0x60198dd0: 28%
0 of 32752 at 0x601a0dc0: 28%
0 of 32752 at 0x601a8db0: 29%
0 of 32752 at 0x601b0da0: 30%
0 of 32752 at 0x601b8d90: 31%
0 of 32752 at 0x601c0d80: 32%
0 of 32752 at 0x601c8d70: 32%
0 of 32752 at 0x601d0d60: 33%
0 of 32752 at 0x601d8d50: 34%
0 of 32752 at 0x601e0d40: 35%
0 of 32752 at 0x601e8d30: 36%
0 of 32752 at 0x601f0d20: 36%
0 of 32752 at 0x601f8d10: 37%
0 of 32752 at 0x60200d00: 38%
0 of 32752 at 0x60208cf0: 39%
0 of 32752 at 0x60210ce0: 40%
0 of 32752 at 0x60218cd0: 40%
0 of 32752 at 0x60220cc0: 41%
0 of 32752 at 0x60228cb0: 42%
0 of 32752 at 0x60230ca0: 43%
0 of 32752 at 0x60238c90: 44%
0 of 32752 at 0x60240c80: 45%
0 of 32752 at 0x60248c70: 45%
0 of 32752 at 0x60250c60: 46%
0 of 32752 at 0x60258c50: 47%
0 of 32752 at 0x60260c40: 48%
0 of 32752 at 0x60268c30: 49%
0 of 32752 at 0x60270c20: 49%
0 of 32752 at 0x60278c10: 50%
0 of 32752 at 0x60280c00: 51%
0 of 32752 at 0x60288bf0: 52%
0 of 32752 at 0x60290be0: 53%
0 of 32752 at 0x60298bd0: 53%
0 of 32752 at 0x602a0bc0: 54%
0 of 32752 at 0x602a8bb0: 55%
0 of 32752 at 0x602b0ba0: 56%
0 of 32752 at 0x602b8b90: 57%
0 of 32752 at 0x602c0b80: 57%
0 of 32752 at 0x602c8b70: 58%
0 of 32752 at 0x602d0b60: 59%
0 of 32752 at 0x602d8b50: 60%
0 of 32752 at 0x602e0b40: 61%
0 of 32752 at 0x602e8b30: 61%
0 of 32752 at 0x602f0b20: 62%
0 of 32752 at 0x602f8b10: 63%
0 of 32752 at 0x60300b00: 64%
0 of 32752 at 0x60308af0: 65%
0 of 32752 at 0x60310ae0: 65%
0 of 32752 at 0x60318ad0: 66%
0 of 32752 at 0x60320ac0: 67%
0 of 32752 at 0x60328ab0: 68%
0 of 32752 at 0x60330aa0: 69%
0 of 32752 at 0x60338a90: 69%
0 of 32752 at 0x60340a80: 70%
0 of 32752 at 0x60348a70: 71%
0 of 32752 at 0x60350a60: 72%
0 of 32752 at 0x60358a50: 73%
0 of 32752 at 0x60360a40: 73%
0 of 32752 at 0x60368a30: 74%
0 of 32752 at 0x60370a20: 75%
0 of 32752 at 0x60378a10: 76%
0 of 32752 at 0x60380a00: 77%
0 of 32752 at 0x603889f0: 77%
0 of 32752 at 0x603909e0: 78%
0 of 32752 at 0x603989d0: 79%
0 of 32752 at 0x603a09c0: 80%
0 of 32752 at 0x603a89b0: 81%
0 of 32752 at 0x603b09a0: 81%
0 of 32752 at 0x603b8990: 82%
0 of 32752 at 0x603c0980: 83%
0 of 32752 at 0x603c8970: 84%
0 of 32752 at 0x603d0960: 85%
0 of 32752 at 0x603d8950: 85%
0 of 32752 at 0x603e0940: 86%
0 of 32752 at 0x603e8930: 87%
0 of 32752 at 0x603f0920: 88%
0 of 32752 at 0x603f8910: 89%
0 of 32752 at 0x60400900: 90%
0 of 32752 at 0x604088f0: 90%
0 of 32752 at 0x604108e0: 91%
0 of 32752 at 0x604188d0: 92%
0 of 32752 at 0x604208c0: 93%
0 of 32752 at 0x604288b0: 94%
0 of 32752 at 0x604308a0: 94%
0 of 32752 at 0x60438890: 95%
0 of 32752 at 0x60440880: 96%
0 of 32752 at 0x60448870: 97%
0 of 32752 at 0x60450860: 98%
0 of 32752 at 0x60458850: 98%
0 of 14300 at 0x60460840: 99%
Finished: 99%
info: Cortex_R5_0: Writing 1 chunk at offset 0x81000
info: Cortex_R5_0: Writing 2 chunk at offset 0x91000
info: Cortex_R5_0: Writing 3 chunk at offset 0xa1000
info: Cortex_R5_0: Writing 4 chunk at offset 0xb1000
info: Cortex_R5_0: Writing 5 chunk at offset 0xc1000
info: Cortex_R5_0: Writing 6 chunk at offset 0xd1000
info: Cortex_R5_0: Writing 7 chunk at offset 0xe1000
info: Cortex_R5_0: Writing 8 chunk at offset 0xf1000
info: Cortex_R5_0: Writing 9 chunk at offset 0x101000
info: Cortex_R5_0: Writing 10 chunk at offset 0x111000
info: Cortex_R5_0: Writing 11 chunk at offset 0x121000
info: Cortex_R5_0: Writing 12 chunk at offset 0x131000
info: Cortex_R5_0: Writing 13 chunk at offset 0x141000
info: Cortex_R5_0: Writing 14 chunk at offset 0x151000
info: Cortex_R5_0: Writing 15 chunk at offset 0x161000
info: Cortex_R5_0: Writing 16 chunk at offset 0x171000
info: Cortex_R5_0: Writing 17 chunk at offset 0x181000
info: Cortex_R5_0: Writing 18 chunk at offset 0x191000
info: Cortex_R5_0: Writing 19 chunk at offset 0x1a1000
info: Cortex_R5_0: Writing 20 chunk at offset 0x1b1000
info: Cortex_R5_0: Writing 21 chunk at offset 0x1c1000
info: Cortex_R5_0: Writing 22 chunk at offset 0x1d1000
info: Cortex_R5_0: Writing 23 chunk at offset 0x1e1000
info: Cortex_R5_0: Writing 24 chunk at offset 0x1f1000
info: Cortex_R5_0: Writing 25 chunk at offset 0x201000
info: Cortex_R5_0: Writing 26 chunk at offset 0x211000
info: Cortex_R5_0: Writing 27 chunk at offset 0x221000
info: Cortex_R5_0: Writing 28 chunk at offset 0x231000
info: Cortex_R5_0: Writing 29 chunk at offset 0x241000
info: Cortex_R5_0: Writing 30 chunk at offset 0x251000
info: Cortex_R5_0: Writing 31 chunk at offset 0x261000
info: Cortex_R5_0: Writing 32 chunk at offset 0x271000
info: Cortex_R5_0: Writing 33 chunk at offset 0x281000
info: Cortex_R5_0: Writing 34 chunk at offset 0x291000
info: Cortex_R5_0: Writing 35 chunk at offset 0x2a1000
info: Cortex_R5_0: Writing 36 chunk at offset 0x2b1000
info: Cortex_R5_0: Writing 37 chunk at offset 0x2c1000
info: Cortex_R5_0: Writing 38 chunk at offset 0x2d1000
info: Cortex_R5_0: Writing 39 chunk at offset 0x2e1000
info: Cortex_R5_0: Writing 40 chunk at offset 0x2f1000
info: Cortex_R5_0: Writing 41 chunk at offset 0x301000
info: Cortex_R5_0: Writing 42 chunk at offset 0x311000
info: Cortex_R5_0: Writing 43 chunk at offset 0x321000
info: Cortex_R5_0: Writing 44 chunk at offset 0x331000
info: Cortex_R5_0: Writing 45 chunk at offset 0x341000
info: Cortex_R5_0: Writing 46 chunk at offset 0x351000
info: Cortex_R5_0: Writing 47 chunk at offset 0x361000
info: Cortex_R5_0: Writing 48 chunk at offset 0x371000
info: Cortex_R5_0: Writing 49 chunk at offset 0x381000
info: Cortex_R5_0: Writing 50 chunk at offset 0x391000
info: Cortex_R5_0: Writing 51 chunk at offset 0x3a1000
info: Cortex_R5_0: Writing 52 chunk at offset 0x3b1000
info: Cortex_R5_0: Writing 53 chunk at offset 0x3c1000
info: Cortex_R5_0: Writing 54 chunk at offset 0x3d1000
info: Cortex_R5_0: Writing 55 chunk at offset 0x3e1000
info: Cortex_R5_0: Writing 56 chunk at offset 0x3f1000
info: Cortex_R5_0: Writing 57 chunk at offset 0x401000
info: Cortex_R5_0: Writing 58 chunk at offset 0x411000
info: Cortex_R5_0: Writing 59 chunk at offset 0x421000
info: Cortex_R5_0: Writing 60 chunk at offset 0x431000
info: Cortex_R5_0: Writing 61 chunk at offset 0x441000
info: Cortex_R5_0: Writing 62 chunk at offset 0x451000
info: Cortex_R5_0: Writing 63 chunk at offset 0x461000
error: Cortex_R5_0: Error Code 40000001
error: Cortex_R5_0: Error Loading the data...
error: Cortex_R5_0: Run failed...
error: Cortex_R5_0: File Loader: Failed to terminate flash programming: Algorithm indicated it failed to flash the data
Failed: File: HWCAPP/user_files/images/MyProgram_HWC_0804_1.appimage: Load failed.

I would also like to provide some additional information about our hardware and Flash Programmer configuration.

Our custom board uses a flash memory IC from the same series as the one installed on the evaluation board, but with a different capacity. The part number of the flash memory used on our custom board is IS25LX128.

Therefore, we use a customized Flash Programmer in which we have modified parameters such as the buffer size. The details are described below.

We found an issue in the flasher_jtag_uniflash_am263px-lp_r5fss0-0_nortos_ti-arm-clang project included in SDK 9.2. When the project is used without modification, an error indicating that the buffer size is insufficient occurs.

However, we confirmed that the flash programming operation completes successfully after modifying main.c as shown in the code below.

//#undef FLASH_WRITE_SECTOR
#define FLASH_WRITE_SECTOR

//#define BOOTLOADER_UNIFLASH_MAX_FILE_SIZE (0x28000) /* This has to match the size of MSRAM1 section in linker.cmd */
//uint8_t gFileBuf[BOOTLOADER_UNIFLASH_MAX_FILE_SIZE] __attribute__((aligned(128), section(".bss.filebuf")));

#define BOOTLOADER_UNIFLASH_MAX_FILE_SIZE (0x10000)
uint8_t gFileBuf[BOOTLOADER_UNIFLASH_MAX_FILE_SIZE+BOOTLOADER_UNIFLASH_HEADER_SIZE] __attribute__((aligned(128), section(".bss.filebuf")));

In addition, because of an issue where the flash_io example in SDK 9.2 does not operate correctly, we made the following changes:

Copied board.c from the flash_io example in SDK 10.1 and added it to the flash_io example in SDK 9.2.
Added board_flash_reset() to main.c.

I apologize if your engineering team has already investigated this point, but I also checked the reported error code in the following header file:

\mcu_plus_sdk_am263px_09_02_00_56\source\drivers\bootloader\bootloader_uniflash.h

The error code is defined as shown below:

#define BOOTLOADER_UNIFLASH_STATUSCODE_FLASH_VERIFY_ERROR (0x40000001)

If there are any additional checks or debugging steps that we can perform in our environment, please let us know. We will be happy to provide further information or logs.

Best regards,

IMADA

0 Ki 13 days ago in reply to ATSUKI IMADA

TI__Guru**** 486931 points

Imada-san,

ATSUKI IMADA said:
As you suggested, I set the timeout value using the command-line argument when running DSLite. However, I confirmed that the same error still occurs even with the increased timeout value.

The timeout suggestion was for Aswin's specific timeout issue. I did not expect it to address your verification issue.

There is current active internal discussion with key engineering people. We hope to have more answer for you soon.

Thank you

Arm-based microcontrollers

Arm-based microcontrollers forum

UNIFLASH: Although the UniFlash standalone command-line log reports a write failure, the program starts successfully.

SBL

APPIMAGE

Log when the process stops midway (1st attempt)

Log when the application boots successfully

Verification Environment

SBL

APPIMAGE

SBL(sbl_ospi_am263px-lp_r5fss0-0_nortos_ti-arm-clang.tiimage)

APPIMAGE(hello_world_am263px-lp_r5fss0-0_nortos_ti-arm-clang.appimage)