AM2434: GPMC timing parameters setting issue

Hello Kashish Thakur,

Thank you for your query !

Refer the below screenshotted example in the AM64x/AM243x GPMC E2E thread:

(+) AM6442: GPMC access to FPGA, write success, read fail - Processors forum - Processors - TI E2E support forums

Although related to an A/D multiplexed synchronous NOR Flash interfaced FPGA (and yours is for an asynchronous non-multiplexed attached NAND), the example refers to the common rules for defining timing parameters of the different GPMC hw interface signals.

For more information on how NAND protocol timings are defined you can refer to the different subsections of the AM64x/AM243x Datasheet / GPMC and NAND Flash — Asynchronous Mode and AM64x / AM243x TRM / Section, NAND Memory Device in Byte or 16-bit Word Stream Mode

I will try to follow up tomorrow (COB) with further comments on your configuration and parameters.

Best Regards,

Anastas Yordanov 

Hello Kashish Thakur,

Sorry for the big time gap in my response.

I haven't got a feedback from you so far. I just wanted to check if you already had the chance to experiment with some of the AM6442 GPMC timing parameter values in the Sysconfig and on board with the postconfig-  generated code. 

I would like to apologize if the example E2E thread with GPMC Synchronous communication timings: [FAQ] Tips for configuring Sitara GPMC registers - Processors forum - Processors - TI E2E support forums might have lead to confusion for some of the parameters. I am clarifying now with our GPMC hardware expert which of the calculations remain the same and which are invalid for an asynchronous non-multiplexed NAND configuration.   

Please let me know if the topic is still actual for you and we shall continue the discussion or we shall rather close this thread ?

Thank you !

Best Regards,

Anastas Yordanov

we calculated the timing parameters according to the formulas which you have given but there is no improvement in the NAND Flash

Hi Kashish,

Sorry if the recommended calculations myside did not have the desired impact.

Is it possible to provide your calculated values ?

I will follow-up with more information or additional questions tomorrow.

Thanks

Best Regards,

Anastas Yordanov 

Hi Kashish,

as promised I am getting back to you with further points.

There are some essential points regarding importance of the  GPMC_CONFIG1_1 - GPMC_CONFIG4_7  setup values for the GPMC NAND interface mode of operation of your MT29F8G08ABACAWP-IT-C. 

Please refer the following sections of the AM64x/AM243x TRM / Section, GPMC NAND Access Description subsections:

The Section, Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode of the AM64x/AM243x TRM states that the MT29F8G08ABACAWP-IT-C timing parameters / modes shall be considered when initializing the: GPMC_CONFIG1_1 through GPMC_CONFIG4_1 bitfield control values, as follows:

You GPMC_CONFIG1_1 (CS1) parameters should be OK for a NAND Flash memory interface in Byte mode.

There are some particular rules that sofwtare shall take into account when performing accesses to the 8-bit NAND flash, as per the Section, NAND Device Command and Address Phase Control of the TRM:

The Command cycles related parameters are covered in the Section, Command Latch Cycle of the TRM:

The connectivity between the involved signals during a command cycle and responsible bitfields can be inferred from the timing diagram:

The choice shall be aligned with the interfaced MT29F8G08ABACAWP-IT-C device specific timing values.

For the Address latch cycle, the involved settings vs address phase timings relation is shown in the NAND Address Latch Cycle timing diagram under the TRM subsection, Address Latch Cycle of  the Section, GPMC NAND Access Description

For the NAND data write or read phase specific timings and involved GPMC_CONFIG1_1 - GPMC_CONFIG1_6 bitfields you may want to refer to the Section, NAND Device Data Read and Write Phase Control in Stream Mode of the TRM.

Can you shortly describe what are the exact timing issues you currently observe when interfacing the NAND with your (corrected according my previous posted formulaes)  Sysconfig GPMC driver configuration ?

Looking forward to your calculated values with which you had no success and answer to my above question ?

Thanks

Best Regards,

Anastas Yordanov

the issue is we are not able to receive the ready busy signal.We probed the lines using logic analyzer and no response on the ready busy signal.The 0xFFh was going to the NAND flash and rest of the CS and other signals were as expected.If our calculated values are wrong then please provide exact values.We are not able to know this is a hardware issue or configuration issue as this is a custom board.