Part Number: AM2612
Other Parts Discussed in Thread: UNIFLASH
Hi experts,
The customer encountered a verification failure during the XIP programming process.
Here is the log
Executing default command:
> dslite --mode flash -c user_files/configs/AM261x.ccxml -l user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -e -f -v "user_files/images/sbl_ospi_multicore_elf_am261x-lp_r5fss0-0_nortos_ti-arm-clang.tiimage,0x60000000" "user_files/images/littlefs_5mV3.3.2.bin,0x60300000" "user_files/images/ethernetip_adapter_generic_device_mii_demo_am261x-lp_r5fss0-0_freertos_ti-arm-clang.mcelf,0x60081000" "user_files/images/ethernetip_adapter_generic_device_mii_demo_am261x-lp_r5fss0-0_freertos_ti-arm-clang.mcelf_xip,0xE0000000"
DSLite version 20.4.0.3973
Configuring Debugger (may take a few minutes on first launch)...
Initializing Register Database...
Initializing: DEBUGSSM_0
Executing Startup Scripts: DEBUGSSM_0
Initializing: CS_DAP_0
Executing Startup Scripts: CS_DAP_0
Initializing: Cortex_R5_0
Executing Startup Scripts: Cortex_R5_0
Initializing: Cortex_R5_1
Executing Startup Scripts: Cortex_R5_1
Initializing: Cortex_M4_0
Executing Startup Scripts: Cortex_M4_0
Initializing: ICSSM0_PRU_0
Executing Startup Scripts: ICSSM0_PRU_0
Initializing: ICSSM0_PRU_1
Executing Startup Scripts: ICSSM0_PRU_1
Initializing: ICSSM1_PRU_0
Executing Startup Scripts: ICSSM1_PRU_0
Initializing: ICSSM1_PRU_1
Executing Startup Scripts: ICSSM1_PRU_1
Initializing: CSSTM_0
Executing Startup Scripts: CSSTM_0
Initializing: CS_ETB_0
Executing Startup Scripts: CS_ETB_0
Connecting...
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
Cortex_R5_0: GEL Output: AM261x Initialization Scripts Launched.
Please Wait...
Cortex_R5_0: GEL Output: ***AM261x Checks sequence Launched...
Cortex_R5_0: GEL Output: AM261x_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM261x_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x0000000C
Cortex_R5_0: GEL Output: OSPI - 8D (xSPI SFDP) Functional boot mode
Cortex_R5_0: GEL Output: AM261x_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM261x_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000100
Cortex_R5_0: GEL Output: *** R5FSS0 is in Lockstep mode ***
Cortex_R5_0: GEL Output: *** Note:Please call this function for Dual Core switch: Dual_core_switch()
Cortex_R5_0: GEL Output: Control_MMR_Register_Unlock() Launched
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: CONTROLSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: Configure_R5F0() Launched
Cortex_R5_0: GEL Output: ZFG - 13.25 mm x 13.25 mm Package
Cortex_R5_0: GEL Output: ***PLL lock sequence Launched
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete for 500MHZ
Cortex_R5_0: GEL Output: PER PLL Configuration Completed
Cortex_R5_0: GEL Output: ETH PLL Configuration Completed
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output: **Clocks Programmed** R5F=500MHz and SYS_CLK=250MHz
Cortex_R5_0: GEL Output: AM261x R5F running at 500Mhz
Cortex_R5_0: GEL Output: Switch to dual core mode
Cortex_R5_0: GEL Output: AM261x Dual core switch
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: AM261x TCM MEM init Done
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
Cortex_R5_0: GEL Output: *** R5FSS0 is in Dual core mode ***
Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
Cortex_R5_0: GEL Output: RTI0 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: RTI1 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: RTI2 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: RTI3 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
Cortex_R5_0: GEL Output: WDT0 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: WDT1 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (192MHz)
Cortex_R5_0: GEL Output: Enabling OSPI Clocks
Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (166.67MHz)
Cortex_R5_0: GEL Output: OSPI1 Clock Enabled (166.67MHz)
Cortex_R5_0: GEL Output: Enabling ICSSM0/1 Core Clocks
Cortex_R5_0: GEL Output: ICSSM0_CORE Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: ICSSM1_CORE Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling ICSSM0/1 UART0 Clocks
Cortex_R5_0: GEL Output: ICSSM0_UART0 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: ICSSM1_UART0 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: Enabling I2C Clocks
Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling TRACE Clocks
Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling MCAN[0:1] Clocks
Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: Enabling GPMC Clocks
Cortex_R5_0: GEL Output: GPMC Clock Enabled (100MHz)
Cortex_R5_0: GEL Output: Enabling ELM Clocks
Cortex_R5_0: GEL Output: ELM Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (500MHz)
Cortex_R5_0: GEL Output: Enabling CPTS Clocks
Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled for 500MHz PLL Configuration***
info: Cortex_R5_0: AM261x
info: Cortex_R5_0: Board Selected : LP
Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL on program load.
Loading Program: Multiple Files
Preparing ...
0 of 32752 at 0x60000000
0 of 32752 at 0x60007ff0
0 of 32752 at 0x6000ffe0: 1%
0 of 32752 at 0x60017fd0: 1%
0 of 32752 at 0x6001ffc0: 2%
0 of 32752 at 0x60027fb0: 2%
0 of 32752 at 0x6002ffa0: 3%
0 of 32752 at 0x60037f90: 3%
0 of 32752 at 0x6003ff80: 4%
0 of 32752 at 0x60047f70: 4%
0 of 29756 at 0x6004ff60: 5%
0 of 32752 at 0x60081000: 5%
info: Cortex_R5_0: Writing 1 chunk at offset 0x0
0 of 32752 at 0x60088ff0: 6%
0 of 32752 at 0x60090fe0: 6%
0 of 32752 at 0x60098fd0: 7%
0 of 32752 at 0x600a0fc0: 7%
0 of 32752 at 0x600a8fb0: 8%
0 of 32752 at 0x600b0fa0: 8%
0 of 32752 at 0x600b8f90: 9%
0 of 32752 at 0x600c0f80: 9%
0 of 32752 at 0x600c8f70: 10%
0 of 32752 at 0x600d0f60: 10%
0 of 32752 at 0x600d8f50: 11%
0 of 32752 at 0x600e0f40: 12%
0 of 32752 at 0x600e8f30: 12%
0 of 32752 at 0x600f0f20: 13%
0 of 32752 at 0x600f8f10: 13%
0 of 32752 at 0x60100f00: 14%
0 of 32752 at 0x60108ef0: 14%
0 of 32752 at 0x60110ee0: 15%
0 of 23592 at 0x60118ed0: 15%
0 of 32752 at 0x60300000: 16%
info: Cortex_R5_0: Writing 1 chunk at offset 0x81000
0 of 32752 at 0x60307ff0: 16%
0 of 32752 at 0x6030ffe0: 17%
0 of 32752 at 0x60317fd0: 17%
0 of 32752 at 0x6031ffc0: 18%
0 of 32752 at 0x60327fb0: 18%
0 of 32752 at 0x6032ffa0: 19%
0 of 32752 at 0x60337f90: 19%
0 of 32752 at 0x6033ff80: 20%
0 of 32752 at 0x60347f70: 20%
0 of 32752 at 0x6034ff60: 21%
0 of 32752 at 0x60357f50: 21%
0 of 32752 at 0x6035ff40: 22%
0 of 32752 at 0x60367f30: 22%
0 of 32752 at 0x6036ff20: 23%
0 of 32752 at 0x60377f10: 23%
0 of 32752 at 0x6037ff00: 24%
0 of 32752 at 0x60387ef0: 24%
0 of 32752 at 0x6038fee0: 25%
0 of 32752 at 0x60397ed0: 26%
0 of 32752 at 0x6039fec0: 26%
0 of 32752 at 0x603a7eb0: 27%
0 of 32752 at 0x603afea0: 27%
0 of 32752 at 0x603b7e90: 28%
0 of 32752 at 0x603bfe80: 28%
0 of 32752 at 0x603c7e70: 29%
0 of 32752 at 0x603cfe60: 29%
0 of 32752 at 0x603d7e50: 30%
0 of 32752 at 0x603dfe40: 30%
0 of 32752 at 0x603e7e30: 31%
0 of 32752 at 0x603efe20: 31%
0 of 32752 at 0x603f7e10: 32%
0 of 32752 at 0x603ffe00: 32%
0 of 32752 at 0x60407df0: 33%
0 of 32752 at 0x6040fde0: 33%
0 of 32752 at 0x60417dd0: 34%
0 of 32752 at 0x6041fdc0: 34%
0 of 32752 at 0x60427db0: 35%
0 of 32752 at 0x6042fda0: 35%
0 of 32752 at 0x60437d90: 36%
0 of 32752 at 0x6043fd80: 37%
0 of 32752 at 0x60447d70: 37%
0 of 32752 at 0x6044fd60: 38%
0 of 32752 at 0x60457d50: 38%
0 of 32752 at 0x6045fd40: 39%
0 of 32752 at 0x60467d30: 39%
0 of 32752 at 0x6046fd20: 40%
0 of 32752 at 0x60477d10: 40%
0 of 32752 at 0x6047fd00: 41%
0 of 32752 at 0x60487cf0: 41%
0 of 32752 at 0x6048fce0: 42%
0 of 32752 at 0x60497cd0: 42%
0 of 32752 at 0x6049fcc0: 43%
0 of 32752 at 0x604a7cb0: 43%
0 of 32752 at 0x604afca0: 44%
0 of 32752 at 0x604b7c90: 44%
0 of 32752 at 0x604bfc80: 45%
0 of 32752 at 0x604c7c70: 45%
0 of 32752 at 0x604cfc60: 46%
0 of 32752 at 0x604d7c50: 46%
0 of 32752 at 0x604dfc40: 47%
0 of 32752 at 0x604e7c30: 48%
0 of 32752 at 0x604efc20: 48%
0 of 32752 at 0x604f7c10: 49%
0 of 32752 at 0x604ffc00: 49%
0 of 32752 at 0x60507bf0: 50%
0 of 32752 at 0x6050fbe0: 50%
0 of 32752 at 0x60517bd0: 51%
0 of 32752 at 0x6051fbc0: 51%
0 of 32752 at 0x60527bb0: 52%
0 of 32752 at 0x6052fba0: 52%
0 of 32752 at 0x60537b90: 53%
0 of 32752 at 0x6053fb80: 53%
0 of 32752 at 0x60547b70: 54%
0 of 32752 at 0x6054fb60: 54%
0 of 32752 at 0x60557b50: 55%
0 of 32752 at 0x6055fb40: 55%
0 of 32752 at 0x60567b30: 56%
0 of 32752 at 0x6056fb20: 56%
0 of 32752 at 0x60577b10: 57%
0 of 32752 at 0x6057fb00: 58%
0 of 32752 at 0x60587af0: 58%
0 of 32752 at 0x6058fae0: 59%
0 of 32752 at 0x60597ad0: 59%
0 of 32752 at 0x6059fac0: 60%
0 of 32752 at 0x605a7ab0: 60%
0 of 32752 at 0x605afaa0: 61%
0 of 32752 at 0x605b7a90: 61%
0 of 32752 at 0x605bfa80: 62%
0 of 32752 at 0x605c7a70: 62%
0 of 32752 at 0x605cfa60: 63%
0 of 32752 at 0x605d7a50: 63%
0 of 32752 at 0x605dfa40: 64%
0 of 32752 at 0x605e7a30: 64%
0 of 32752 at 0x605efa20: 65%
0 of 32752 at 0x605f7a10: 65%
0 of 32752 at 0x605ffa00: 66%
0 of 32752 at 0x606079f0: 66%
0 of 32752 at 0x6060f9e0: 67%
0 of 32752 at 0x606179d0: 67%
0 of 32752 at 0x6061f9c0: 68%
0 of 32752 at 0x606279b0: 69%
0 of 32752 at 0x6062f9a0: 69%
0 of 32752 at 0x60637990: 70%
0 of 32752 at 0x6063f980: 70%
0 of 32752 at 0x60647970: 71%
0 of 32752 at 0x6064f960: 71%
0 of 32752 at 0x60657950: 72%
0 of 32752 at 0x6065f940: 72%
0 of 32752 at 0x60667930: 73%
0 of 32752 at 0x6066f920: 73%
0 of 32752 at 0x60677910: 74%
0 of 32752 at 0x6067f900: 74%
0 of 32752 at 0x606878f0: 75%
0 of 32752 at 0x6068f8e0: 75%
0 of 32752 at 0x606978d0: 76%
0 of 32752 at 0x6069f8c0: 76%
0 of 32752 at 0x606a78b0: 77%
0 of 32752 at 0x606af8a0: 77%
0 of 32752 at 0x606b7890: 78%
0 of 32752 at 0x606bf880: 78%
0 of 32752 at 0x606c7870: 79%
0 of 32752 at 0x606cf860: 80%
0 of 32752 at 0x606d7850: 80%
0 of 32752 at 0x606df840: 81%
0 of 32752 at 0x606e7830: 81%
0 of 32752 at 0x606ef820: 82%
0 of 32752 at 0x606f7810: 82%
0 of 32752 at 0x606ff800: 83%
0 of 32752 at 0x607077f0: 83%
0 of 32752 at 0x6070f7e0: 84%
0 of 32752 at 0x607177d0: 84%
0 of 32752 at 0x6071f7c0: 85%
0 of 32752 at 0x607277b0: 85%
0 of 32752 at 0x6072f7a0: 86%
0 of 32752 at 0x60737790: 86%
0 of 32752 at 0x6073f780: 87%
0 of 32752 at 0x60747770: 87%
0 of 32752 at 0x6074f760: 88%
0 of 32752 at 0x60757750: 88%
0 of 32752 at 0x6075f740: 89%
0 of 32752 at 0x60767730: 89%
0 of 32752 at 0x6076f720: 90%
0 of 32752 at 0x60777710: 91%
0 of 32752 at 0x6077f700: 91%
0 of 32752 at 0x607876f0: 92%
0 of 32752 at 0x6078f6e0: 92%
0 of 32752 at 0x607976d0: 93%
0 of 32752 at 0x6079f6c0: 93%
0 of 32752 at 0x607a76b0: 94%
0 of 32752 at 0x607af6a0: 94%
0 of 32752 at 0x607b7690: 95%
0 of 32752 at 0x607bf680: 95%
0 of 32752 at 0x607c7670: 96%
0 of 32752 at 0x607cf660: 96%
0 of 32752 at 0x607d7650: 97%
0 of 32752 at 0x607df640: 97%
0 of 32752 at 0x607e7630: 98%
0 of 32752 at 0x607ef620: 98%
0 of 32752 at 0x607f7610: 99%
0 of 2560 at 0x607ff600: 99%
0 of 208 at 0xe0000000: 99%
Finished: 99%
info: Cortex_R5_0: Writing 1 chunk at offset 0x300000
info: Cortex_R5_0: Writing 2 chunk at offset 0x400000
info: Cortex_R5_0: Writing 3 chunk at offset 0x500000
info: Cortex_R5_0: Writing 4 chunk at offset 0x600000
info: Cortex_R5_0: Writing 5 chunk at offset 0x700000
Setting PC to entry point.: 99%
Verifying Program: Multiple Files
Preparing ...
0 of 32752 at 0x60000000
0 of 32752 at 0x60007ff0
0 of 32752 at 0x6000ffe0: 1%
0 of 32752 at 0x60017fd0: 1%
0 of 32752 at 0x6001ffc0: 2%
0 of 32752 at 0x60027fb0: 2%
0 of 32752 at 0x6002ffa0: 3%
0 of 32752 at 0x60037f90: 3%
0 of 32752 at 0x6003ff80: 4%
0 of 32752 at 0x60047f70: 4%
0 of 29756 at 0x6004ff60: 5%
0 of 32752 at 0x60081000: 5%
0 of 32752 at 0x60088ff0: 6%
0 of 32752 at 0x60090fe0: 6%
0 of 32752 at 0x60098fd0: 7%
0 of 32752 at 0x600a0fc0: 7%
0 of 32752 at 0x600a8fb0: 8%
0 of 32752 at 0x600b0fa0: 8%
0 of 32752 at 0x600b8f90: 9%
0 of 32752 at 0x600c0f80: 9%
0 of 32752 at 0x600c8f70: 10%
0 of 32752 at 0x600d0f60: 10%
0 of 32752 at 0x600d8f50: 11%
0 of 32752 at 0x600e0f40: 12%
0 of 32752 at 0x600e8f30: 12%
0 of 32752 at 0x600f0f20: 13%
0 of 32752 at 0x600f8f10: 13%
0 of 32752 at 0x60100f00: 14%
0 of 32752 at 0x60108ef0: 14%
0 of 32752 at 0x60110ee0: 15%
0 of 23592 at 0x60118ed0: 15%
0 of 32752 at 0x60300000: 16%
0 of 32752 at 0x60307ff0: 16%
0 of 32752 at 0x6030ffe0: 17%
0 of 32752 at 0x60317fd0: 17%
0 of 32752 at 0x6031ffc0: 18%
0 of 32752 at 0x60327fb0: 18%
0 of 32752 at 0x6032ffa0: 19%
0 of 32752 at 0x60337f90: 19%
0 of 32752 at 0x6033ff80: 20%
0 of 32752 at 0x60347f70: 20%
0 of 32752 at 0x6034ff60: 21%
0 of 32752 at 0x60357f50: 21%
0 of 32752 at 0x6035ff40: 22%
0 of 32752 at 0x60367f30: 22%
0 of 32752 at 0x6036ff20: 23%
0 of 32752 at 0x60377f10: 23%
0 of 32752 at 0x6037ff00: 24%
0 of 32752 at 0x60387ef0: 24%
0 of 32752 at 0x6038fee0: 25%
0 of 32752 at 0x60397ed0: 26%
0 of 32752 at 0x6039fec0: 26%
0 of 32752 at 0x603a7eb0: 27%
0 of 32752 at 0x603afea0: 27%
0 of 32752 at 0x603b7e90: 28%
0 of 32752 at 0x603bfe80: 28%
0 of 32752 at 0x603c7e70: 29%
0 of 32752 at 0x603cfe60: 29%
0 of 32752 at 0x603d7e50: 30%
0 of 32752 at 0x603dfe40: 30%
0 of 32752 at 0x603e7e30: 31%
0 of 32752 at 0x603efe20: 31%
0 of 32752 at 0x603f7e10: 32%
0 of 32752 at 0x603ffe00: 32%
0 of 32752 at 0x60407df0: 33%
0 of 32752 at 0x6040fde0: 33%
0 of 32752 at 0x60417dd0: 34%
0 of 32752 at 0x6041fdc0: 34%
0 of 32752 at 0x60427db0: 35%
0 of 32752 at 0x6042fda0: 35%
0 of 32752 at 0x60437d90: 36%
0 of 32752 at 0x6043fd80: 37%
0 of 32752 at 0x60447d70: 37%
0 of 32752 at 0x6044fd60: 38%
0 of 32752 at 0x60457d50: 38%
0 of 32752 at 0x6045fd40: 39%
0 of 32752 at 0x60467d30: 39%
0 of 32752 at 0x6046fd20: 40%
0 of 32752 at 0x60477d10: 40%
0 of 32752 at 0x6047fd00: 41%
0 of 32752 at 0x60487cf0: 41%
0 of 32752 at 0x6048fce0: 42%
0 of 32752 at 0x60497cd0: 42%
0 of 32752 at 0x6049fcc0: 43%
0 of 32752 at 0x604a7cb0: 43%
0 of 32752 at 0x604afca0: 44%
0 of 32752 at 0x604b7c90: 44%
0 of 32752 at 0x604bfc80: 45%
0 of 32752 at 0x604c7c70: 45%
0 of 32752 at 0x604cfc60: 46%
0 of 32752 at 0x604d7c50: 46%
0 of 32752 at 0x604dfc40: 47%
0 of 32752 at 0x604e7c30: 48%
0 of 32752 at 0x604efc20: 48%
0 of 32752 at 0x604f7c10: 49%
0 of 32752 at 0x604ffc00: 49%
0 of 32752 at 0x60507bf0: 50%
0 of 32752 at 0x6050fbe0: 50%
0 of 32752 at 0x60517bd0: 51%
0 of 32752 at 0x6051fbc0: 51%
0 of 32752 at 0x60527bb0: 52%
0 of 32752 at 0x6052fba0: 52%
0 of 32752 at 0x60537b90: 53%
0 of 32752 at 0x6053fb80: 53%
0 of 32752 at 0x60547b70: 54%
0 of 32752 at 0x6054fb60: 54%
0 of 32752 at 0x60557b50: 55%
0 of 32752 at 0x6055fb40: 55%
0 of 32752 at 0x60567b30: 56%
0 of 32752 at 0x6056fb20: 56%
0 of 32752 at 0x60577b10: 57%
0 of 32752 at 0x6057fb00: 58%
0 of 32752 at 0x60587af0: 58%
0 of 32752 at 0x6058fae0: 59%
0 of 32752 at 0x60597ad0: 59%
0 of 32752 at 0x6059fac0: 60%
0 of 32752 at 0x605a7ab0: 60%
0 of 32752 at 0x605afaa0: 61%
0 of 32752 at 0x605b7a90: 61%
0 of 32752 at 0x605bfa80: 62%
0 of 32752 at 0x605c7a70: 62%
0 of 32752 at 0x605cfa60: 63%
0 of 32752 at 0x605d7a50: 63%
0 of 32752 at 0x605dfa40: 64%
0 of 32752 at 0x605e7a30: 64%
0 of 32752 at 0x605efa20: 65%
0 of 32752 at 0x605f7a10: 65%
0 of 32752 at 0x605ffa00: 66%
0 of 32752 at 0x606079f0: 66%
0 of 32752 at 0x6060f9e0: 67%
0 of 32752 at 0x606179d0: 67%
0 of 32752 at 0x6061f9c0: 68%
0 of 32752 at 0x606279b0: 69%
0 of 32752 at 0x6062f9a0: 69%
0 of 32752 at 0x60637990: 70%
0 of 32752 at 0x6063f980: 70%
0 of 32752 at 0x60647970: 71%
0 of 32752 at 0x6064f960: 71%
0 of 32752 at 0x60657950: 72%
0 of 32752 at 0x6065f940: 72%
0 of 32752 at 0x60667930: 73%
0 of 32752 at 0x6066f920: 73%
0 of 32752 at 0x60677910: 74%
0 of 32752 at 0x6067f900: 74%
0 of 32752 at 0x606878f0: 75%
0 of 32752 at 0x6068f8e0: 75%
0 of 32752 at 0x606978d0: 76%
0 of 32752 at 0x6069f8c0: 76%
0 of 32752 at 0x606a78b0: 77%
0 of 32752 at 0x606af8a0: 77%
0 of 32752 at 0x606b7890: 78%
0 of 32752 at 0x606bf880: 78%
0 of 32752 at 0x606c7870: 79%
0 of 32752 at 0x606cf860: 80%
0 of 32752 at 0x606d7850: 80%
0 of 32752 at 0x606df840: 81%
0 of 32752 at 0x606e7830: 81%
0 of 32752 at 0x606ef820: 82%
0 of 32752 at 0x606f7810: 82%
0 of 32752 at 0x606ff800: 83%
0 of 32752 at 0x607077f0: 83%
0 of 32752 at 0x6070f7e0: 84%
0 of 32752 at 0x607177d0: 84%
0 of 32752 at 0x6071f7c0: 85%
0 of 32752 at 0x607277b0: 85%
0 of 32752 at 0x6072f7a0: 86%
0 of 32752 at 0x60737790: 86%
0 of 32752 at 0x6073f780: 87%
0 of 32752 at 0x60747770: 87%
0 of 32752 at 0x6074f760: 88%
0 of 32752 at 0x60757750: 88%
0 of 32752 at 0x6075f740: 89%
0 of 32752 at 0x60767730: 89%
0 of 32752 at 0x6076f720: 90%
0 of 32752 at 0x60777710: 91%
0 of 32752 at 0x6077f700: 91%
0 of 32752 at 0x607876f0: 92%
0 of 32752 at 0x6078f6e0: 92%
0 of 32752 at 0x607976d0: 93%
0 of 32752 at 0x6079f6c0: 93%
0 of 32752 at 0x607a76b0: 94%
0 of 32752 at 0x607af6a0: 94%
0 of 32752 at 0x607b7690: 95%
0 of 32752 at 0x607bf680: 95%
0 of 32752 at 0x607c7670: 96%
0 of 32752 at 0x607cf660: 96%
0 of 32752 at 0x607d7650: 97%
0 of 32752 at 0x607df640: 97%
0 of 32752 at 0x607e7630: 98%
0 of 32752 at 0x607ef620: 98%
0 of 32752 at 0x607f7610: 99%
0 of 2560 at 0x607ff600: 99%
0 of 208 at 0xe0000000: 99%
error: Cortex_R5_0: File Loader: Verification failed: Values at address 0xE0000000 do not match (expected: 0x7F, actual: 0xD0) Please verify target memory and memory map.
Finished: 99%
Failed: File: Multiple Files: a data verification error occurred, file load failed.
============================================================
[ FAILED ] FLASH PROGRAMMING FAILED 1
============================================================
Press any key to continue....
Dslite File:
@echo off
setlocal
setlocal ENABLEDELAYEDEXPANSION
REM Path to this batch script
set UNIFLASH_PATH=%~dp0
REM Path to DebugServer folder
set DEBUGSERVER_ROOT=%~dp0ccs_base\DebugServer\
set MODE=flash
set EXECUTABLE="!DEBUGSERVER_ROOT!bin\DSLite"
set GENERATED_COMMAND=-c user_files/configs/AM261x.ccxml -l user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -e -f -v "user_files/images/sbl_ospi_multicore_elf_am261x-lp_r5fss0-0_nortos_ti-arm-clang.tiimage,0x60000000" "user_files/images/littlefs_5mV3.3.2.bin,0x60300000" "user_files/images/ethernetip_adapter_generic_device_mii_demo_am261x-lp_r5fss0-0_freertos_ti-arm-clang.mcelf,0x60081000" "user_files/images/ethernetip_adapter_generic_device_mii_demo_am261x-lp_r5fss0-0_freertos_ti-arm-clang.mcelf_xip,0xE0000000"
set ADDITIONALS=
REM list available modes
if "%1"=="--listMode" (
echo.
echo Usage: dslite --mode ^<mode^> arg
echo.
echo Available Modes for UniFlash CLI:
echo * flash [default] - on-chip flash programming
echo * memory - export memory to a file
echo * load - simple loader [use default options]
echo * serial - serial flash programming
echo * noConnectFlash - bypasses connect sequence during flash; for programming a blank CC23xx device
if exist !DEBUGSERVER_ROOT!drivers\MSP430Flasher.exe (
echo * mspflasher - support MSPFlasher command line parameters [deprecated]
)
exit /b 0
)
REM no parameters given, use the default generated command
if "%1" EQU "" (
echo Executing default command:
echo ^> dslite --mode !MODE! !GENERATED_COMMAND! !ADDITIONALS!
echo.
CMD /S /C "%EXECUTABLE% !MODE! !GENERATED_COMMAND! !ADDITIONALS!"
set FLASH_RC=!errorlevel!
echo.
if !FLASH_RC! EQU 0 (
echo ============================================================
echo ============================================================
echo ============================================================
echo ============================================================
echo [ SUCCESS ] FLASH PROGRAMMING COMPLETED SUCCESSFULLY!
echo ============================================================
echo ============================================================
echo ============================================================
echo ============================================================
) else (
echo ============================================================
echo [ FAILED ] FLASH PROGRAMMING FAILED! ERROR CODE: !FLASH_RC!
echo ============================================================
)
echo.
pause
exit /b !FLASH_RC!
)
REM user options parsing
set USEROPTIONS=%*
REM user options without the --mode
set "_args=%*"
set "_args=!_args:*%1 =!"
set "_args=!_args:*%2 =!"
if "%3"=="" (
set USEROPTIONS2=
) else (
set USEROPTIONS2=!_args!
)
REM custom mode from users
if "%1" EQU "--mode" (
set MODE=%2
set USEROPTIONS=!USEROPTIONS2!
)
REM default user options if none given
if "!USEROPTIONS!" EQU "" (
set USEROPTIONS=-h
)
REM mspflasher support
if "%MODE%" EQU "mspflasher" (
set EXECUTABLE=!DEBUGSERVER_ROOT!drivers\MSP430Flasher.exe
set MODE=
)
REM execute with given user parameters
echo Executing the following command:
if "!MODE!" EQU "" (
echo ^> !EXECUTABLE! !USEROPTIONS! !ADDITIONALS!
) else (
echo ^> !EXECUTABLE! !MODE! !USEROPTIONS! !ADDITIONALS!
)
echo.
echo For more details and examples, please visit software-dl.ti.com/.../latest_qsguide.html
echo.
CMD /S /C "%EXECUTABLE% !MODE! !USEROPTIONS! !ADDITIONALS!"
exit /b !errorlevel!I instructed the client to use the following command:
set GENERATED_COMMAND=-c user_files/configs/AM261x.ccxml -l user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -e -f "user_files/images/sbl_ospi_multicore_elf_am261x-lp_r5fss0-0_nortos_ti-arm-clang.tiimage,0x60000000" "user_files/images/littlefs_5mV3.3.2.bin,0x60300000" "user_files/images/ethernetip_adapter_generic_device_mii_demo_am261x-lp_r5fss0-0_freertos_ti-arm-clang.mcelf,0x60081000" "user_files/images/ethernetip_adapter_generic_device_mii_demo_am261x-lp_r5fss0-0_freertos_ti-arm-clang.mcelf_xip,0xE0000000"
This effectively disables the verification step.
Customer feedback: After removing the verification step, the program can be correctly flashed. Furthermore, upon power-cycling the chip, the CPU is able to properly execute the program located in the XIP (eXecute-In-Place) region.
The question now is why verification fails in UniFlash.
Thanks
