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Hi Anthony,
I got a strange problem. I want use GIOB[2] as a input. But I can not got the value of this pin.
For GIOB[2], I have gated off the Emif_CLK in HCG(HALCoGen 03.05.02). I changed the level of the pin through hardware and read the value by the code showed below, but it did not change. Because this is a specific, I maybe make some mistakes.
Would you help me to find the problem.
void gioInit(void)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
/** bring GIO module out of reset */
gioREG->GCR0 = 1U;
gioREG->INTENACLR = 0xFFU;
gioREG->LVLCLR = 0xFFU;
/** @b initialize @b Port @b A */
/** - Port A output values */
gioPORTA->DOUT = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** - Port A direction */
gioPORTA->DIR = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** - Port A open drain enable */
gioPORTA->PDR = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** - Port A pullup / pulldown selection */
gioPORTA->PSL = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (1U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** - Port A pullup / pulldown enable*/
gioPORTA->PULDIS = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (1U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** @b initialize @b Port @b B */
/** - Port B output values */
gioPORTB->DOUT = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** - Port B direction */
gioPORTB->DIR = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** - Port B open drain enable */
gioPORTB->PDR = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** - Port B pullup / pulldown selection */
gioPORTB->PSL = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (1U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/** - Port B pullup / pulldown enable*/
gioPORTB->PULDIS = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U); /* Bit 7 */
/* USER CODE BEGIN (3) */
/* USER CODE END */
/** @b initialize @b interrupts */
/** - interrupt polarity */
gioREG->POL = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (1U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U) /* Bit 7 */
| (0U << 8U) /* Bit 8 */
| (0U << 9U) /* Bit 9 */
| (1U << 10U)/* Bit 10 */
| (0U << 11U)/* Bit 11 */
| (0U << 12U)/* Bit 12 */
| (0U << 13U)/* Bit 13 */
| (0U << 14U)/* Bit 14 */
| (0U << 15U)/* Bit 15 */
/** - interrupt level */
gioREG->LVLSET = 0U /* Bit 0 */
| (0U << 1U) //* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (0U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U) /* Bit 7 */
| (0U << 8U) /* Bit 8 */
| (0U << 9U) /* Bit 9 */
| (0U << 10U)/* Bit 10 */
| (0U << 11U)/* Bit 11 */
| (0U << 12U)/* Bit 12 */
| (0U << 13U)/* Bit 13 */
| (0U << 14U)/* Bit 14 */
| (0U << 15U)/* Bit 15 */
/** - clear all pending interrupts */
gioREG->FLG = 0xFFU;
/** - enable interrupts */
gioREG->INTENASET = 0U /* Bit 0 */
| (0U << 1U) /* Bit 1 */
| (0U << 2U) /* Bit 2 */
| (0U << 3U) /* Bit 3 */
| (0U << 4U) /* Bit 4 */
| (1U << 5U) /* Bit 5 */
| (0U << 6U) /* Bit 6 */
| (0U << 7U) /* Bit 7 */
| (0U << 8U) /* Bit 8 */
| (0U << 9U) /* Bit 9 */
| (0U << 10U)/* Bit 10 */
| (0U << 11U)/* Bit 11 */
| (0U << 12U)/* Bit 12 */
| (0U << 13U)/* Bit 13 */
| (0U << 14U)/* Bit 14 */
| (0U << 15U)/* Bit 15 */
/* USER CODE BEGIN (4) */
/* USER CODE END */
}
uint32 keybufferL;
...........
void main (void)
{
/* USER CODE BEGIN (3) */
/* user_ initialization */
rtiInit();
gioInit();
.........
keybufferL = 0;
/*user main loop*/
while(1)
{
......
keybufferL = gioGetPort(gioPORTB);
......
}
/* USER CODE END */
}
Thanks,
B.Rs,
Chuan
Chuan,
Most likely - this is due to GIOB[2] being available on 2 different pads:
There is an input multiplex selection register that controls which pad drives GIOB[2].
The mux is described on page 228 of SPNU499b:
Most likely if you see the GIOB[2] state changing in the pin but not in the memory mapped DIN register, then this mux is set wrong for your application.
Chuan,
Sorry, for RM48L952, the equivalent document is SPNU503B. That is the TRM for the RM48 series.
Pin 142 is the default for GIOB[2] so you should be ok reading from this pin, unless you have changed the default somewhere (e.x. in a HalCoGen configuration).
EDIT: We noticed an error in the TRM description for GIOB[2]; it lists PINMMR29[16] twice where this isn't true.
The truth table for the input mux selection of GIOB[2] (reorganized slightly) should look like this:
Thanks to Sunil Oak for catching this.
Hi Chuan,
First though the TRM / SPNU503B is linked here. Also you can always search for keyword 'spnu503' at www.ti.com. Just make sure it's a keyword search not a part # search.
#1 is fine.
#2 - This: "use giob_2 for disabling selection HET2 PMW output" and connected the GIOB2 at pin55 " is for something else. See below if you want to understand but it's not part of the GIOB[2] pin location choice.
I think the problem is like you said - you shouldn't have PIN 55 set ot GIOB[2] if you want GIOB[2] to read from pin 142. I think this can get confusing because you'd like to see GIOB[2] on this pinmux sheet, but it's the only function for pin 142 therefore pin 142 isn't listed on the PINMUX page in HalCoGen..
Please double check the PINMMR registers 9 and 29 when your code runs though - to make sure they are like the previous post says. That I think is more direct than looking at the generated code.
#3 GIOB does have interrupt capability; I also see it show up in HalCoGen. I'm not sure I understand the problem/question. Would you please explain more?
Thanks and Best Regards,
Anthony
-------
#2 again - this is what the "use giob_2 for disabling selection HET2 PMW output" and connected the GIOB2 at pin55 " is for...
Hi Anthony,
Before your last post, I just read the SPNU499. So I thought the GIOB have not interrupt. The PSNU503B is a right document.
I have tried to remove the GIOB form PIN55 in HalCoGen, but nothing be changed in the code.
I read the code which was generated by HalCoGen. the pinmmx9 and pinmmx29 were setup in "void muxInit(void)".
It is showed below.
pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_PIN_54_HET1_31 | PINMUX_PIN_55_MIBSPI3NCS_0;
pinMuxReg->PINMMR29 = 0x01010101U;
Form the setup. The pinmmr9[18] (GIOB2) is reversed. If it's initial value is "1". After the Muxinit(), it will be cleared to '0". The pinmmr29[16] is setup to "1". According to "The input to a module comes from the dedicated pad when the condition [ not(A) or (A and B) ] = TRUE."(from page 221 of SPNU503B), A = pinmmr9[18], B= pinmmr29[16]. So not(A) =true or (A and B) = false, that means GIOB2 should come from pin142. But it still do not works. The register is showed below. I found there is a error in register Srs of GIOB which is " UNABLE TO READ". Do you know what is problem here.
PINMMR9[18] and PINMMR29[16]:
GIOB Register: I connect "GND" to pin142, but the Din[2] =1
At the table 4-16 in page 234 of SPNU503B, the pinmmr29[16] instead of the pinmmr9[18]. and at the table 4-1 in page 221 of SPNU503B, the pinmmr29[16] also stead of the pinmmr9[18] in column of "Control Register Bit A". If does the GIOB2 connect to pin 142 only be controlled by pimm29[16]?
If that is not true, I do not understand the initial setup of pinmmr9[18]. Why does pinmmr9[18] be reversed in the Muxinit()?
Thanks,
B.Rs,
Chuan
