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Do GIOB[0] and GIOB[1] are disconnected in RM48HDK?

matteo lucarelli
Genius 3265 points
Other Parts Discussed in Thread: HALCOGEN

Hi,

I'm working with RM48HDK. Testing the GIO functionality with a simple project I cannot see GIOB[0] and GIOB[1] working, both as input or as output.

I've enable all the GIO pins in the HalCoGen MUX table. All other pins (GIOA[0] to [7] and GIOB [2] to [7]) works as expected but the GIOB[0] and GIOB[1] seems disconnected.

Any suggestion?

Thank you

  • 0
    TI__Guru 68820 points

    Matteo,

    GIOB0 and GIOB1 are switched on the HDK between the USB Phy and the connector J11.

    See sheet 11, the CBT Component.    The CBT component is controlled by the DIP switch S2.

    You might have "USB ON" selected on that dip switch which would break the connection to J11.

  • 0 in reply to Anthony F. Seely
    Genius 3265 points

    You suggestion goes in the right direction. DIP switch are involved but not in the way you suggest:

    - GIOB[0] and GIOB[1] are disconnected enabling the ethernet DIP switch

    - GIOB[3] receive a pwm by enabling USB host1 or USB device DIP switch

    Since I have to use the ethernet I have to give GIOB[0] and GIOB[1].

    Thank you,

    Matteo


  • 0 in reply to matteo lucarelli
    TI__Guru 68820 points

    Matteo,

    I see.  Yes you are correct.

    I think that since you have USB_HOST_ON = H and ETHERNET_ON = L, you will be making the connection on U10

    from A -> B3.   When this connection is made,  the GIOB1 and GIOB0 pins are NC on U10.   So if you have the ability to jumper U10-12 and U10-14 to U10-44 and U10-42 then you could probably have these available on the connector when ethernet is on.

    However, this would be a mod on a fine pitch SMD component so you might not want to try it.   In any case this issue w. GIOB0, GIOB1 is a board limitation not a chip limitation;  so you could have them back if you make your own board design.