• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 491 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM4 CRC CPU Full Mode

Anton Reinhardt
Prodigy 10 points

My first post .

Awesome  is the Hercules Safety CPU .

Have one question :

I have not been successful trying to learn the CRC timing specs, How many clock cycles to perform one 32bit or 64bit calculation?

I have seen the following in one of ti's example code :

for(i=0U;i<param->data_length;i++)
{
switch (param->crc_channel)
{
case 0U:
crc->PSA_SIGREGL1= *ptr32++;
crc->PSA_SIGREGH1= *ptr32++;
break;
case 1U:
crc->PSA_SIGREGL2= *ptr32++;
crc->PSA_SIGREGH2= *ptr32++;
break;
default :
break;
}
}

This C loop implies that no checking for hardware completion is perform after each write operation. Therefore I must assume that the operation completes in only a few clock cycles .  True ?

Regards

Anton Reinhardt

 

  • 0
    TI__Guru 59540 points

    Hello Anton and welcome to the Hercules Forum. I hope you find it useful.

    You are correct that the writes to the registers will take only a few cycles to complete. Also, when there are a series of writes like this, after the first write is initiated, subsequent writes will be held off until the first write is completed. This is handled by the architecture within the device. If this answers your question, please click the verify button so that others can see that the answer was sufficient for you. If not, please let me know and I will clarify or add additional information.