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CCS/RM46L850: RM4

rock
Intellectual 760 points
Part Number: RM46L850
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

Hi !!! I want to know why two PLL configuration is required for EMAC_LOOP_TXRX.

  • 0
    TI__Guru**** 192486 points

    Hello Rakesh,

    The EMAC internal logic is clocked synchronously on the VCLKA4. The MDIO clock is based on a divide-down of the VCL3.

    VCLK3 is the peripheral clock divided down from HCLK which is from PLL1 or PLL2

    VCLKA4 can be from VCLK or from PLL1 or PLL2.

    You can use only PLL1 for this example. PLL2 is the 2nd option for tis example.

  • 0 in reply to QJ Wang
    Intellectual 760 points

    thanks Wang for your valuable reply. still have a query.

    HOW can I customize the VCLKA4 in R46xxPGE.

    But in R4xxZWT the divider VCLKA4 divider is present.(GCM mode)

  • 0 in reply to rock
    TI__Guru**** 192486 points

    Hello,

    I think you use an old version HALCOGen? The GCM in HALCoGen 4.07.01 is different from yours.