CCS/RM46L850: RM4

Hello Rakesh,

The EMAC internal logic is clocked synchronously on the VCLKA4. The MDIO clock is based on a divide-down of the VCL3.

VCLK3 is the peripheral clock divided down from HCLK which is from PLL1 or PLL2

VCLKA4 can be from VCLK or from PLL1 or PLL2.

You can use only PLL1 for this example. PLL2 is the 2nd option for tis example.

thanks Wang for your valuable reply. still have a query.

HOW can I customize the VCLKA4 in R46xxPGE.

But in R4xxZWT the divider VCLKA4 divider is present.(GCM mode)