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CAN Initialization, IF1 does not write to message RAM

Timm Richlick
Prodigy 200 points
Other Parts Discussed in Thread: RM46L852, RM48L952, HALCOGEN, TMS570LS3137, RM48L950

Hi,

as I narrowed the previous problem from my last thread, I think it makes sense to start a new topic.

I'm using Keil and a RM46L852. I try to initialize message box 1 via the IF1 register using the following code (after setting the init bit in the CTL register):

canREG2->IF1MSK  = 0xDFFC0000U; // 110|11111111111|000000000000000000 (MXtd = 1, MDir = 1, Msk = 7FFh)
canREG2->IF1ARB  = (uint32)0x80000000U | (((uint32)15U) << 18U); // 100|00000001111|000000000000000000 (MsgVal = 1, ID = 15)
canREG2->IF1MCTL = 0x00001080U | (uint32)8U; // 100001000|1000 (UMask = 1, EoB = 1, DLC = 8)
canREG2->IF1CMD  = (uint8) 0xF8U; // 11111000 (WR/RD = 1, Mask = 1, Arb = 1, Control = 1, ClrIntPnd = 1)
canREG2->IF1NO   = 1U; // START COPY PROCESS: 001 (Message Number = 1)
while ((canREG2->IF1STAT & 0x80U) == 0x80U) {} // WAIT TILL IF1 IS READY

After this I expect the message box 1 to be configured and therefore check the MsgVal value (should be 1 as set in IF1ARB):

if(canREG2->MSGVALx[0] == 0) return false; // CHECK IF FIRST MESSAGE BOXES ARE VALID

This will always return false, hence I suspect that IF1 is not writing the message box configuration into the message RAM.

I was suspecting that maybe Keil is somehow putting the RM46 into debug mode so that the IF1/2 registers are not working anymore. Or that the RM46 is in a certain safety mode where the IF1/2 registers are not working.

Many thanks in advance,
Timm

  • 0
    Mastermind 7585 points

    Could it be that you mismatch extended and standard ID? You initialized MXtd = 1, however your Mask is set to Msk = 0x7FF and ID (15) is shifted 18 times to match 11 bit identifiers.

     

  • 0 in reply to Frank Bormann
    Prodigy 200 points

    Hi Frank,

    thank you for your answer! As far as I understood the MXtd bit is just saying that the IDE bit in the CAN message will also be used for acceptance filtering (so that extended CAN messages will be filtered out for this message box, only standard CAN messages will be received). I set the Xtd bit in IF1ARB to zero, so standard frames are used.

    Anyhow, I also tried this out (MXtd = 0) but without a difference, the MsgVal bit isn't set.

    I also tried to use the Direct Access Memory Mode to directly write into the message RAM (without using IF1/2). Unfortunately in this mode it is not possible to set the MsgVal bit in the message RAM for a certain message box. It is simply not included in the memory mapping. Don't ask me why.

    Greetings,

    Timm

  • 0 in reply to Timm Richlick
    Mastermind 7585 points

    Hi Timm,

    sorry my mistake, of course MXtd is just filtering the IDE bit of the message.

    So let's try a next step: what is the status of register canREG2->CTL, before you execute the ID2 - instructions from above? In my cases it is 0x31443 and after writing to IF2NO register MsgVal12 immediately shows a 3 (3 because I have also initialized mailbox1 with IF1 just before IF2. 

    When I remove all my IF1-code from the test, MsgVal12 = 2 and MsgValX = 1 after instruction canREG2->IF2NO=2; has been executed.

     

     

     

     

     

  • 0 in reply to Frank Bormann
    Prodigy 200 points

    Hi Frank,

    canREG2->CTL is in my case 0x21443 (I'm not entering debug mode). Strange behavior: if I try to enter debug mode (canREG2->CTL = 0x31443) it is getting refused and the register shows afterwards the value 0x21443. I don't no if this is relevant.

    Unfortunately my MsgVal registers keep being zero after the IF2NO instruction. Do you also use a RM46L852? Is there any chance you could send me your code example? What kind of software environment are you using?

    Thanks,

    Timm

  • 0 in reply to Timm Richlick
    Mastermind 7585 points

    Hi Timm,

    I use TMS570LS3137, RM48L950 and RM48L952, software environment is CCS5.4 plus HalCogen 3.05.02, hardware platforms are the HDK's. 

    I have attached a "getting started" - PDF, taken from my customer workshop material. It starts with HalCoGen to produce the code framework and continues with CCS to create the project and modify the code.  Objective is to setup DCAN1 at 100 kbit/s with mailbox1 (transmit ID 0x12000000 every 100 ms) and mailbox2 (receive ID 0x10000000). Payload of mailbox 1 is an incremental 1-byte pattern. The 1st byte of a received message is dsiplayed with its 3 LSB's at 3 HET-LED'S of the HDK.

     

     

    RM48HDK_Lab3_2(DCAN1 transmit and receive).pdf
  • 0 in reply to Frank Bormann
    Prodigy 200 points

    Hi Frank,

    I was finally able to solve this problem. I found out that Keil uVision is NOT compatible with the RM46, it will lock the controller in debug mode in such a way that the CAN module stops working (but reading/writing CAN registers is possible). I'm now using CCS and it is working.

    I've never expected the dev environment to be the problem.

    Thanks anyhow for your help!

    Greetings, Timm