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Silicon Errate

Mark Blay
Intellectual 370 points
Other Parts Discussed in Thread: TMS570LS20206

I am using the TMS570LS20206 with ARM optimising C compiler v4.9.

I am looking at errate CORTEX-R4#46 & CORTEX-R4#55

In relation to these errate, if the -mv7R4 option is specified on the compile line, can it be assumed that the conditions defined are avoided by the compiler? In other words do these errate only really need to be considered when assembly code is being written manually?

Thanks,

Mark.

  • 0
    TI__Guru**** 192666 points

    Hi Mark,

    -mv7R4 won't avoid the conditions in errata #55 and #66.

    #55: the advanced SIMD functionality is determined by reading the part number from the ID registers rather than examining ASEDIS and D32DIS in the CPACR.

    #66: Please set the sMOV bit in Auxiliary Control Register. #66 is valid for both the assembly code written manually or the assembly code generated by the compiler.

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Intellectual 370 points

    Hi QJ, thanks for your response.

    I think unfortunately I am now a little more confused. So just considering #55, are you saying that when the compiler is presented with C code including floating point operations it will insert instructions to read from the ID register to determine whether the high registers can be used rather than determining it from the command line switch that tells it what processor it is compiling for?

    I can understand if I was writing assembly language to be portable across a number of processors I would use the ID register to determine availability of advanced SIMD functionality, I just don't understand why a compiler would do this. I admit to not being very familiar with the inner workings of compilers so would like to gain a better understanding of the mechanisms used.

    Thanks for any further clarification,

    Mark.