tms570ls0432 - het-pwm duty cycle update

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; This example will illustrate a simple asymmetrical PWM generation. The duty cycle
; is to be updated by the host CPU by writing the new duty cycle (compare value) to 
; the MOV32 data field. When there is a compare match, the MOV32 instruction will move
; the new compare value to the ECMP instruction. The update of the ECMP is considered
; synchronous as the update is only done with respect to the LRP (loop resolution period)
; and only when there is a compare match.
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PWM_PERIOD            .equ 100
PWM_PIN_NUM           .equ 9
INIT_COMPARE          .equ 50
INIT_HR_DELAY         .equ 0

; PWM with synchronous duty cycle update at compare match event
L00   CNT { reg=A,irq=ON,max=PWM_PERIOD};
L01   ECMP { next=L03,hr_lr=HIGH,en_pin_action=ON,cond_addr=L02,pin=PWM_PIN_NUM,action=PULSELO,reg=A,irq=OFF,data=INIT_COMPARE,hr_data=INIT_HR_DELAY};
L02   MOV32 { remote=L01,type=IMTOREG&REM,reg=NONE,data=INIT_COMPARE,hr_data=INIT_HR_DELAY};
L03   BR { next= L00, cond_addr=L00, event= NOCOND }