Host Bus 16-bit Muxed Interface Using EPI on TM4C129

ler

Other Parts Discussed in Thread: TM4C129XNCZAD

Hello. I have reviewed Figure 11-11 in the product data sheet for the TM4C129XNCZAD part. From this drawing, it would appear that additions latches are necessary to de-mux the address and data lines for the EPI0-EPI15 lines. Is this correct? I am guessing for example that the signal A0 is a de-muxed version of EPI0.

Any help or examples of external memory for this part would be helpful.

Thank you.

ler

over 10 years ago

0 Amit Ashara over 10 years ago

TI__Guru**** 244400 points

Hello Ier,

Yes. If the external memory device does not support a ALE then external latches are required. There is a TI Design with external memory interfacing like Async RAM and Flash that is slated to come out soon. However I can help with the details if required. If the question is about what external latch then I have used two SN74LV373APWR

Regards
Amit

0 ler over 10 years ago in reply to Amit Ashara

Expert 1070 points

Thanks Amit. This is quite helpful and I believe I can draw this up. I would like to see the TI Design once it comes out.

ler

0 Amit Ashara over 10 years ago in reply to ler

TI__Guru**** 244400 points

Hello Ier,

I think the processing of the documents, schematics, layout and gerbers, etc will take upto a month. In the meantime I can help if there are any issues/care-abouts that you may be looking for

Regards
Amit

0 ler over 10 years ago in reply to Amit Ashara

Expert 1070 points

Proposed schematic for external SRAM using EPIO interface. Will something like this work?Amit.docx

0 Amit Ashara over 10 years ago in reply to ler

TI__Guru**** 244400 points

Hello Ier,

Looks fine to me. Make sure that for every supply pin you have the 0.1uF cap placed close to the VCC pin of the device. In case of SRAM that would be 2 caps.

Regards
Amit

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Host Bus 16-bit Muxed Interface Using EPI on TM4C129